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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-12-04 17:38:46 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-12-06 18:59:53 +0000 |
| commit | 65783fbeb4d2b8180165b36083023f94bdccbdb7 (patch) | |
| tree | 8a36732e4cd150917d051cbfd438c9f1a633f924 /src/soc/intel/jasperlake | |
| parent | 2f5c7590770f7bbb00f899a1495675083872b0d7 (diff) | |
soc/amd/cezanne: use common TSC and monotonic timer code
Change-Id: I9bc82f1e64f2cf21bfa4bf1ac75d17247208686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48306
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake')
0 files changed, 0 insertions, 0 deletions