diff options
| author | Martin Roth <martin@coreboot.org> | 2020-07-24 12:26:21 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-07-26 21:21:03 +0000 |
| commit | c25c1ebd9ed54d9c70d4c247c71fc19259751413 (patch) | |
| tree | d68c85a2ea48572c40b42c223cfbbcd922012fcb /src/soc/intel/jasperlake | |
| parent | f48acbda7be7074938c06db8ad37705f850661ee (diff) | |
src: Update bare access to BOOL CONFIG_ vals to CONFIG()
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/jasperlake')
| -rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 6493fd590e..cdafae3cc8 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -103,7 +103,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); params->SkipMpInit = 0; } else { - params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; + params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT); } /* Chipset Lockdown */ @@ -123,7 +123,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->EndOfPostMessage = EOP_PEI; /* Legacy 8254 timer support */ - params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER); params->Enable8254ClockGatingOnS3 = 1; /* disable Legacy PME */ |