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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-05 13:58:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-12 08:52:58 +0000 |
| commit | 463e44bedbf3d5f24b8e6e19475b5155b523309a (patch) | |
| tree | fb682224271ad976c42b992c01444a7f64aca31c /src/soc/intel/jasperlake | |
| parent | 52082be9d6065de40d5354868f884c0c454d86dc (diff) | |
security/intel/txt: Add and use DPR register layout
This simplifies operations with this register's bitfields, and can also
be used by TXT-enabled platforms on the register in PCI config space.
Change-Id: I10a26bc8f4457158dd09e91d666fb29ad16a2087
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46050
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake')
0 files changed, 0 insertions, 0 deletions