diff options
| author | Ben Kao <ben.kao@intel.com> | 2021-07-04 21:24:36 +0800 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2021-07-26 05:00:51 +0000 |
| commit | 6eb52534513beda06e7787ee550c02198a447d5c (patch) | |
| tree | 7c3eed5fc4fec5f853354de506152e1ec074fecc /src/soc/intel/jasperlake/xhci.c | |
| parent | 3b28ab098ec1e7f1ffadb335f110b584a82e83f5 (diff) | |
soc/intel/jasperlake: Set xHCI LFPS period sampling off time
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/xhci.c')
| -rw-r--r-- | src/soc/intel/jasperlake/xhci.c | 43 |
1 files changed, 42 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/xhci.c b/src/soc/intel/jasperlake/xhci.c index eebacca9eb..75663795d3 100644 --- a/src/soc/intel/jasperlake/xhci.c +++ b/src/soc/intel/jasperlake/xhci.c @@ -1,13 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <device/pci_type.h> +#include <console/console.h> +#include <device/mmio.h> #include <intelblocks/xhci.h> +#include <soc/soc_chip.h> #define XHCI_USB2_PORT_STATUS_REG 0x480 #define XHCI_USB3_PORT_STATUS_REG 0x500 #define XHCI_USB2_PORT_NUM 8 #define XHCI_USB3_PORT_NUM 6 +#define XHCI_PMCTRL 0x80A4 +/* BIT[7:4] LFPS periodic sampling off time for USB3 Ports */ +#define PMCTRL_LFPS_OFFTIME_SHIFT 4 +#define PMCTRL_LFPS_OFFTIME_MAX 0xF + static const struct xhci_usb_info usb_info = { .usb2_port_status_reg = XHCI_USB2_PORT_STATUS_REG, .num_usb2_ports = XHCI_USB2_PORT_NUM, @@ -20,3 +27,37 @@ const struct xhci_usb_info *soc_get_xhci_usb_info(pci_devfn_t xhci_dev) /* Jasper Lake only has one XHCI controller */ return &usb_info; } + +static void set_xhci_lfps_sampling_offtime(struct device *dev, uint8_t time_ms) +{ + void *addr; + const struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + + if (!res) + return; + + if (time_ms > PMCTRL_LFPS_OFFTIME_MAX) { + printk(BIOS_ERR, + "XHCI: The maximum LFPS sampling OFF time is %u ms, " + "cannot set it to %u ms\n", + PMCTRL_LFPS_OFFTIME_MAX, time_ms); + + return; + } + + addr = (void *)(uintptr_t)(res->base + XHCI_PMCTRL); + clrsetbits32(addr, + PMCTRL_LFPS_OFFTIME_MAX << PMCTRL_LFPS_OFFTIME_SHIFT, + time_ms << PMCTRL_LFPS_OFFTIME_SHIFT); + printk(BIOS_DEBUG, + "XHCI: Updated LFPS sampling OFF time to %u ms\n", time_ms); +} + +void soc_xhci_init(struct device *dev) +{ + const config_t *config = config_of_soc(); + + /* Set xHCI LFPS period sampling off time */ + set_xhci_lfps_sampling_offtime(dev, + config->xhci_lfps_sampling_offtime_ms); +} |