diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-04-30 12:23:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-01 06:56:45 +0000 |
| commit | 7be0df8dd354d87c2482ac2d2cca29628297bd03 (patch) | |
| tree | bff5e3633287ab339eee5a2521415fc42ef60939 /src/soc/intel/jasperlake/romstage | |
| parent | 1d17529954fda73460ef2441706139967e3a6b78 (diff) | |
soc/intel/{jsl,tgl}: Rename PcdDebugInterfaceFlags macros for better understanding
BIT 1 -> DEBUG_INTERFACE_UART_8250IO
BIT 4 -> DEBUG_INTERFACE_LPSS_SERIAL_IO
Change-Id: I566b9dc82b2289af42e58705ebeee51179886f1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/romstage')
| -rw-r--r-- | src/soc/intel/jasperlake/romstage/fsp_params.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index a841809499..bb7db65dd7 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -60,7 +60,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* Set debug interface flags */ m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ? - DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO; + DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO; /* TraceHub configuration */ dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); |