diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-06-17 16:17:19 +0530 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-07-23 04:54:01 +0000 |
| commit | e8156ad9818111a58e0d54e27b74e083c1d4f856 (patch) | |
| tree | bb7479c44efda11254caec3803085a48d8af2d6c /src/soc/intel/jasperlake/romstage/fsp_params.c | |
| parent | df96d4db84f192e6d3e21f4995d548af84e1df5e (diff) | |
soc/intel/jasperlake: Add the SkipCpuReplacementCheck configuration
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.
BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530
Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/jasperlake/romstage/fsp_params.c')
| -rw-r--r-- | src/soc/intel/jasperlake/romstage/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 6d4055ab51..0688eea3a4 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -114,6 +114,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, ARRAY_SIZE(config->PchHdaAudioLinkSndwEnable), "copy buffer overflow!"); memcpy(m_cfg->PchHdaAudioLinkSndwEnable, config->PchHdaAudioLinkSndwEnable, sizeof(config->PchHdaAudioLinkSndwEnable)); + + /* Skip the CPU replacement check */ + m_cfg->SkipCpuReplacementCheck = config->SkipCpuReplacementCheck; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) |