diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-10-31 22:01:55 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-11-02 10:43:53 +0000 |
| commit | 4ed9f9a507a8b3419bc45431b8f1afb02c728a9e (patch) | |
| tree | e7162cab8a10d65af58b481bb681845d7ae5abbb /src/soc/intel/jasperlake/reset.c | |
| parent | 2b2ade96384791d7320d87bc0e29445002b6d246 (diff) | |
soc/intel: Use of common reset code block
This patch removes all redundant reset code block from each SoC
and make use of common reset code block(fsp_reset.c) based on
SOC_INTEL_COMMON_FSP_RESET.
Respective SoC Kconfig to choose correct FSP global reset type as
per FSP integration guide.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I71531f4cf7a40efa9ec55c48c2cb4fb6ea90531f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/soc/intel/jasperlake/reset.c')
| -rw-r--r-- | src/soc/intel/jasperlake/reset.c | 17 |
1 files changed, 0 insertions, 17 deletions
diff --git a/src/soc/intel/jasperlake/reset.c b/src/soc/intel/jasperlake/reset.c index 1f7ea3c180..bc5815ac7a 100644 --- a/src/soc/intel/jasperlake/reset.c +++ b/src/soc/intel/jasperlake/reset.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cf9_reset.h> -#include <console/console.h> #include <intelblocks/cse.h> #include <intelblocks/pmclib.h> -#include <fsp/util.h> #include <soc/intel/common/reset.h> -#include <soc/pci_devs.h> void do_global_reset(void) { @@ -18,17 +15,3 @@ void do_global_reset(void) pmc_global_reset_enable(1); do_full_reset(); } - -void chipset_handle_reset(uint32_t status) -{ - switch (status) { - case FSP_STATUS_RESET_REQUIRED_3: /* Global Reset */ - printk(BIOS_DEBUG, "GLOBAL RESET!!\n"); - global_reset(); - break; - default: - printk(BIOS_ERR, "unhandled reset type %x\n", status); - die("unknown reset type"); - break; - } -} |