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author | Varshit Pandya <pandyavarshit@gmail.com> | 2024-02-09 18:26:32 +0530 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-12 13:58:32 +0000 |
commit | ef513773abbfd4892f2017f14db818e9b973f8be (patch) | |
tree | 7049f15ca8d6982f59792c20795b354c986d6334 /src/soc/intel/jasperlake/meminit.c | |
parent | ddd002010fe4fe693e7345b490f65ea4bfca0896 (diff) |
soc/amd/picasso: Use pcie_gpp_dxio_update_clk_req_config
This function turns off gpp_clk for the devices which are disabled, and
adds the code to fix up the clock configuration depending on dxio
descriptors. Also this brings picasso in line with cezanne, mendocino
and phoenix. This also prepares picasso to use the common function
gpp_clk_setup_common.
Change-Id: Ice2e3a5a78359da9a438434c7d4aa1eca878d396
Signed-off-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80413
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/meminit.c')
0 files changed, 0 insertions, 0 deletions