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| author | Shuo Liu <shuo.liu@intel.com> | 2024-03-30 00:37:55 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-07 10:20:11 +0000 |
| commit | 0f3316bc71aab50dbd8464ee2fb5b680947f2ca5 (patch) | |
| tree | 171b21354e0fc94c7a2acca3a8dd64e8da6ba6ad /src/soc/intel/jasperlake/meminit.c | |
| parent | 775c0e6de28390ac0d5688bfce1d7437878eb55f (diff) | |
device/device_util: Add and use is_pci_bridge()
TEST=Build and boot on intel/archercity CRB
Change-Id: Ied4921f7dc7e144e580d05d4f2262777aa59d895
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81566
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/meminit.c')
0 files changed, 0 insertions, 0 deletions