diff options
| author | Jędrzej Ciupis <jciupis@google.com> | 2024-08-02 14:38:54 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-22 13:13:47 +0000 |
| commit | 07dd73c9214b766762a89ffe51f27c77799293be (patch) | |
| tree | fec99f9588327d4a6a0db2b400c75a6ea902d558 /src/soc/intel/jasperlake/include | |
| parent | 94a65fa2c6c8922ef9883cc45656a19f994975e5 (diff) | |
soc/intel/jasperlake: Add CrashLog implementation for Intel JSL
Extend support for CrashLog to Intel Jasperlake based platforms.
This commit is based on 15cbc3b5996ae64aff2e4741c4c3ec3d7f5cc1a7,
originally reviewed on https://review.coreboot.org/c/coreboot/+/49943.
BUG=b:354834461
TEST=CrashLog can be enabled in Kconfig for Jasperlake based platforms
and can generate a BERT table, if enabled.
Change-Id: Ia18a79d8de849d556b4b8fd0e6b43090311eb23f
Signed-off-by: Jędrzej Ciupis <jciupis@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/include')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/crashlog.h | 23 | ||||
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/pci_devs.h | 7 |
2 files changed, 30 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/crashlog.h b/src/soc/intel/jasperlake/include/soc/crashlog.h new file mode 100644 index 0000000000..e8ba0aaa10 --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/crashlog.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_ +#define _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_ + +#include <types.h> + +/* DVSEC capability Registers */ +#define TEL_DVSEC_OFFSET 0x100 +#define TEL_DVSEC_PCIE_CAP_ID 0x0 +#define TEL_DVSEC_NEXT_CAP 0x2 +#define TEL_DVSEV_ID 0x8 +#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET 0xC +#define TELEMETRY_EXTENDED_CAP_ID 0x23 +#define CRASHLOG_DVSEC_ID 0x04 +#define TEL_DVSEC_TBIR_BAR0 0 +#define TEL_DVSEC_TBIR_BAR1 1 + +/* CPU CrashLog MMIO Registers */ +#define CRASHLOG_MAILBOX_INTF_ADDRESS 0x6038 +#define CRASHLOG_POINTER_SIZE_FIELD_OFFSET 0x04 + +#endif /* _SOC_JASPERLAKE_BLOCK_CRASHLOG_LIB_H_ */ diff --git a/src/soc/intel/jasperlake/include/soc/pci_devs.h b/src/soc/intel/jasperlake/include/soc/pci_devs.h index e3276458bf..b8cc067a36 100644 --- a/src/soc/intel/jasperlake/include/soc/pci_devs.h +++ b/src/soc/intel/jasperlake/include/soc/pci_devs.h @@ -5,12 +5,15 @@ #include <device/pci_def.h> +#define _SA_DEVFN(slot, func) PCI_DEVFN(SA_DEV_SLOT_ ## slot, func) #define _PCH_DEVFN(slot, func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> +#define _SA_DEV(slot, func) pcidev_path_on_root(_SA_DEVFN(slot, func)) #define _PCH_DEV(slot, func) pcidev_path_on_root_debug(_PCH_DEVFN(slot, func), __func__) #else +#define _SA_DEV(slot, func) PCI_DEV(0, SA_DEV_SLOT_ ## slot, func) #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func) #endif @@ -48,6 +51,10 @@ #define SA_DEVFN_GNA PCI_DEVFN(SA_DEV_SLOT_GNA, 0) #define SA_DEV_GNA PCI_DEV(0, SA_DEV_SLOT_GNA, 0) +#define SA_DEV_SLOT_TMT 0x14 +#define SA_DEVFN_TMT _SA_DEVFN(TMT, 2) +#define SA_DEV_TMT _SA_DEV(TMT, 2) + /* PCH Devices */ #define PCH_DEV_SLOT_SIO0 0x10 #define PCH_DEVFN_CNVI_BT _PCH_DEVFN(SIO0, 2) |