diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-04-30 12:07:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-03 12:21:17 +0000 |
| commit | ffb5811b325c86ee47d283d694a11ef0860706bb (patch) | |
| tree | 084d5ba4f526372f07af375cbb451bc07a74d387 /src/soc/intel/jasperlake/include | |
| parent | e585f5b5cc29b006c551c746fb0bfb5fc69ec358 (diff) | |
soc/intel/jasperlake: Update C-States info
- Update C-States max latency values
- Remove MSR programming for C-States latency
BRANCH=None
TEST=Boot to OS and check CState Latenecy
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048
Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/include')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/cpu.h | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/cpu.h b/src/soc/intel/jasperlake/include/soc/cpu.h index 1e5332de51..c61f2ee95f 100644 --- a/src/soc/intel/jasperlake/include/soc/cpu.h +++ b/src/soc/intel/jasperlake/include/soc/cpu.h @@ -5,13 +5,13 @@ #include <intelblocks/msr.h> -/* Latency times in units of 32768ns */ -#define C_STATE_LATENCY_CONTROL_0_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_1_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_2_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_3_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_4_LIMIT 0x9d -#define C_STATE_LATENCY_CONTROL_5_LIMIT 0x9d +/* Latency times in us */ +#define C1_LATENCY 1 +#define C6_LATENCY 127 +#define C7_LATENCY 253 +#define C8_LATENCY 260 +#define C9_LATENCY 487 +#define C10_LATENCY 1048 /* Power in units of mW */ #define C1_POWER 0x3e8 |