diff options
| author | Jamie Chen <jamie.chen@intel.com> | 2021-07-20 18:33:57 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-28 11:40:27 +0000 |
| commit | 1ebcb2ab62b9fa258b4fe614df70250efebec54a (patch) | |
| tree | 904bc9431bfd8227a60145118f9240d2e3f1bc0c /src/soc/intel/jasperlake/include | |
| parent | 0f93a7b781b220b3bcddf1edabff7c8be52c9aeb (diff) | |
soc/intel/jasperlake: add pcie modphy settings
This patch adds device tree settings to control pcie modphy tuning
FSP UPDs. With this patch, the pcie modphy can be tuned per board.
BUG=b:192716633
BRANCH=NONE
TEST=build dedede variant coreboot with fw_debug enable and check if
these settings have been changed successfully on fsp debug log.
Change-Id: I80a91d45f9dd8ef218846e1284fdad309313e831
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/include')
| -rw-r--r-- | src/soc/intel/jasperlake/include/soc/pcie_modphy.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/include/soc/pcie_modphy.h b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h new file mode 100644 index 0000000000..60f145195f --- /dev/null +++ b/src/soc/intel/jasperlake/include/soc/pcie_modphy.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_JASPERLAKE_PCIE_MODPHY_H_ +#define _SOC_JASPERLAKE_PCIE_MODPHY_H_ + +struct pcie_modphy_config { + /* TX Output Downscale Amplitude Adjustment */ + bool tx_gen1_downscale_amp_override; + uint8_t tx_gen1_downscale_amp; + /* TX Output Downscale Amplitude Adjustment */ + bool tx_gen2_downscale_amp_override; + uint8_t tx_gen2_downscale_amp; + /* TX Output Downscale Amplitude Adjustment */ + bool tx_gen3_downscale_amp_override; + uint8_t tx_gen3_downscale_amp; + /* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */ + uint8_t tx_gen1_de_emph; + /* TX Output -3.5dB Mode De-Emphasis Adjustment Setting */ + uint8_t tx_gen2_de_emph_3p5; + /* TX Output -6.0dB Mode De-Emphasis Adjustment Setting */ + uint8_t tx_gen2_de_emph_6p0; +}; + +#endif |