diff options
author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-09-23 12:43:43 +0530 |
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committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-10-08 19:11:34 +0000 |
commit | 5b3a0ff4f1ac064b3aca61169fbb87a72d4592bd (patch) | |
tree | 0b3e4135c5afddcc8540f437bcdf847a7e7daacc /src/soc/intel/jasperlake/fsp_params.c | |
parent | 11bda4d41cc20b1e3f9798f0f277aaa936b4b6e0 (diff) |
soc/intel/jasperlake: Add VR Configuration settings
This CL fixes the CPU Throttling issue.
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/fsp_params.c')
-rw-r--r-- | src/soc/intel/jasperlake/fsp_params.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index d2e07e9f58..1919936003 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -177,6 +177,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(params->SataPortsDevSlp)); } + /* VR Configuration */ + params->ImonSlope[0] = config->ImonSlope; + params->ImonOffset[0] = config->ImonOffset; + /* SDCard related configuration */ dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); params->ScsSdCardEnabled = is_dev_enabled(dev); |