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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-25 00:02:29 +0000 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-30 00:45:08 +0000 |
| commit | 9f6cdbaaf5d1a799e314e0baf9f4fda218abdf75 (patch) | |
| tree | 7e389d972b2e4dce00382e6c73e20da623e5b759 /src/soc/intel/jasperlake/espi.c | |
| parent | a6f02a8c494a6a8584caf0453a028d76bdd2d972 (diff) | |
Revert "broadwell: update processor power limits configuration"
This reverts commit fa42d568a00e5daadd35722790c529539227130e.
Reason for revert: Passes in an incompatible structure and only happens
to boot by chance. Moreover, Broadwell will soon be merged with Haswell
and this requires Broadwell to not depend on any Intel common SoC code.
Tested on out-of-tree Acer Aspire E5-573, PL values are correct again.
Change-Id: I6e8e000dba8ff09fab4e6f174ab703348dcd6a96
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45011
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/espi.c')
0 files changed, 0 insertions, 0 deletions