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| author | Simon Yang <simon1.yang@intel.com> | 2021-06-22 10:15:20 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-07-28 11:40:45 +0000 |
| commit | df520855ca14095729fdb9a10c26852f397879de (patch) | |
| tree | 9d43607f1970893a1ef18a46482d9017caba6915 /src/soc/intel/jasperlake/chip.h | |
| parent | 1ebcb2ab62b9fa258b4fe614df70250efebec54a (diff) | |
soc/intel/jsl: Add disable_external_bypass_vr config
This dev tree config controls the Vnn/Vcc1P05 bypass mode for Jasperlake.
BUG=b:191691430
BRANCH=dedede
TEST=Build fw and confirm FSP setting are set properly by log
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: I10bc203d3fed32ab65f325978426b7d0fca6f392
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 001597e308..18627f6021 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -403,6 +403,18 @@ struct soc_intel_jasperlake_config { */ uint8_t RampDown; + /* + * It controls below soc variables + * + * PchFivrExtV1p05RailEnabledStates + * PchFivrExtVnnRailSxEnabledStates + * PchFivrExtVnnRailEnabledStates + * + * If your platform does not support external vnn power rail please set to 1 + * 1: Disabled ; 0: Enabled + */ + bool disable_external_bypass_vr; + }; typedef struct soc_intel_jasperlake_config config_t; |