diff options
| author | Meera Ravindranath <meera.ravindranath@intel.com> | 2020-09-23 12:43:43 +0530 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-10-08 19:11:34 +0000 |
| commit | 5b3a0ff4f1ac064b3aca61169fbb87a72d4592bd (patch) | |
| tree | 0b3e4135c5afddcc8540f437bcdf847a7e7daacc /src/soc/intel/jasperlake/chip.h | |
| parent | 11bda4d41cc20b1e3f9798f0f277aaa936b4b6e0 (diff) | |
soc/intel/jasperlake: Add VR Configuration settings
This CL fixes the CPU Throttling issue.
BUG=b:167472333
TEST=Build and boot dedede and observe the slope and offset values
getting updated in the fsp debug log
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I3fa32218040263f0abef8b9dd4c52efb31289fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 6b5f599911..5a87a91037 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -136,6 +136,10 @@ struct soc_intel_jasperlake_config { /* Heci related */ uint8_t Heci3Enabled; + /* VR Config Settings for IA Core */ + uint16_t ImonSlope; + uint16_t ImonOffset; + /* Gfx related */ uint8_t IgdDvmt50PreAlloc; uint8_t InternalGfx; |