diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-08 21:31:44 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-18 07:10:13 +0000 |
| commit | e8d1bef8cbd78c00065381848030655d34d0ecd3 (patch) | |
| tree | 7bea607316e936a8f7370b32689d35ea3c0f0e08 /src/soc/intel/jasperlake/chip.h | |
| parent | 4fafd412090d7de9a2ec6232ed22bbb1b1ce5dde (diff) | |
jasperlake: update processor power limits configuration
Update processor power limit configuration parameters based on
common code base support for Intel Jasperlake SoC based platforms.
BRANCH=None
BUG=None
TEST=Built for jasperlake system
Change-Id: I9b725d041dcb8847f83ec103e58b9571b4c596ac
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/jasperlake/chip.h')
| -rw-r--r-- | src/soc/intel/jasperlake/chip.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index 7a6a7fd0dd..d8ea560dfa 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -7,6 +7,7 @@ #include <intelblocks/cfg.h> #include <intelblocks/gpio.h> #include <intelblocks/gspi.h> +#include <intelblocks/power_limit.h> #include <soc/gpe.h> #include <soc/gpio.h> #include <soc/gpio_defs.h> @@ -26,6 +27,9 @@ struct soc_intel_jasperlake_config { /* Common struct containing soc config data required by common code */ struct soc_intel_common_config common_soc_config; + /* Common struct containing power limits configuration information */ + struct soc_power_limits_config power_limits_config; + /* Gpio group routed to each dword of the GPE0 block. Values are * of the form PMC_GPP_[A:U] or GPD. */ uint8_t pmc_gpe0_dw0; /* GPE0_31_0 STS/EN */ @@ -145,8 +149,6 @@ struct soc_intel_jasperlake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; |