diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-04-30 12:07:16 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-06-03 12:21:17 +0000 |
| commit | ffb5811b325c86ee47d283d694a11ef0860706bb (patch) | |
| tree | 084d5ba4f526372f07af375cbb451bc07a74d387 /src/soc/intel/jasperlake/acpi.c | |
| parent | e585f5b5cc29b006c551c746fb0bfb5fc69ec358 (diff) | |
soc/intel/jasperlake: Update C-States info
- Update C-States max latency values
- Remove MSR programming for C-States latency
BRANCH=None
TEST=Boot to OS and check CState Latenecy
>cat /sys/devices/system/cpu/cpu0/cpuidle/state*/{name,latency}
POLL
C1_ACPI
C2_ACPI
C3_ACPI
0
1
253
1048
Change-Id: I05c0b5b31d1883f72ca94171aa1b536621e97449
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40902
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/jasperlake/acpi.c')
| -rw-r--r-- | src/soc/intel/jasperlake/acpi.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c index 373f95c5c7..88ec5fedd6 100644 --- a/src/soc/intel/jasperlake/acpi.c +++ b/src/soc/intel/jasperlake/acpi.c @@ -52,70 +52,70 @@ enum { static const acpi_cstate_t cstate_map[NUM_C_STATES] = { [C_STATE_C0] = {}, [C_STATE_C1] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 0), }, [C_STATE_C1E] = { - .latency = 0, + .latency = C1_LATENCY, .power = C1_POWER, .resource = MWAIT_RES(0, 1), }, [C_STATE_C6_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 0), }, [C_STATE_C6_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C6_LATENCY, .power = C6_POWER, .resource = MWAIT_RES(2, 1), }, [C_STATE_C7_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 0), }, [C_STATE_C7_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 1), }, [C_STATE_C7S_SHORT_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 2), }, [C_STATE_C7S_LONG_LAT] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C7_LATENCY, .power = C7_POWER, .resource = MWAIT_RES(3, 3), }, [C_STATE_C8] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C8_LATENCY, .power = C8_POWER, .resource = MWAIT_RES(4, 0), }, [C_STATE_C9] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C9_LATENCY, .power = C9_POWER, .resource = MWAIT_RES(5, 0), }, [C_STATE_C10] = { - .latency = C_STATE_LATENCY_FROM_LAT_REG(0), + .latency = C10_LATENCY, .power = C10_POWER, .resource = MWAIT_RES(6, 0), }, }; static int cstate_set_non_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C6_LONG_LAT, C_STATE_C7S_LONG_LAT }; static int cstate_set_s0ix[] = { - C_STATE_C1E, + C_STATE_C1, C_STATE_C7S_LONG_LAT, C_STATE_C10 }; |