soc/intel/jasperlake: Add Jasper Lake SoC support

This is a copy patch from Tiger Lake SoC code.

The only changes done on top of copy is changing below configs:
1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY
2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY
3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY

We started with initial assumption that JSL and TGL can co-exist.
But now we see the SoC code in Tiger Lake is relying on too many
compile-time directives to make two SoCs co-exist. Some of the
differences are listed below:

-> Kconfig: Multiple Kconfig options using
   if SOC_INTEL_{TIGERLAKE/JASPERLAKE}

-> GPIO: GPIO communities have their own differences.
   This requires conditional checks in gpio.asl, gpio.c, gpio*.h,
   pmc.h and gpio.asl

-> PCI IRQs: Set up differently for JSL and TGL

-> PCIe: Number of Root ports differ.

-> eMMC/SD: Only supported on JSL.

-> USB: Number of USB port are different for JSL and TGL.

-> Memory configuration parameters are different for JSL and TGL.

-> FSP parameters for JSL and TGL are different.

The split of JSL and TGL SoC code is planned as below:

1. Copy Tiger Lake SoC code as is, and change SoC Kconfig
   to avoid conflicts with current mainboard builds.

2. Clean up TGL code out of copy patch done in step 1.
   Make it JSL only code. The SoC config still kept as
   SOC_INTEL_JASPERLAKE_COPY.

3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to
   SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can
   bind to SoC code from soc/intel/jasperlake. This step establishes
   Jasper Lake as a separate SoC.

4. Clean up current JSL code from TGL code. This step establishes
   Tiger Lake as a separate SoC.

BUG=b:150217037

Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>

1 files changed, 343 insertions, 0 deletions

diff --git a/src/soc/intel/jasperlake/acpi.c b/src/soc/intel/jasperlake/acpi.c
new file mode 100644
index 0000000000..23fd970500
--- /dev/null
+++ b/src/soc/intel/jasperlake/acpi.c
@@ -0,0 +1,343 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/mmio.h>
+#include <arch/smp/mpspec.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <ec/google/chromeec/ec.h>
+#include <intelblocks/cpulib.h>
+#include <intelblocks/pmclib.h>
+#include <intelblocks/acpi.h>
+#include <soc/cpu.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/soc_chip.h>
+#include <soc/systemagent.h>
+#include <string.h>
+#include <wrdd.h>
+
+/*
+ * List of supported C-states in this processor.
+ */
+enum {
+	C_STATE_C0,		/* 0 */
+	C_STATE_C1,		/* 1 */
+	C_STATE_C1E,		/* 2 */
+	C_STATE_C6_SHORT_LAT,	/* 3 */
+	C_STATE_C6_LONG_LAT,	/* 4 */
+	C_STATE_C7_SHORT_LAT,	/* 5 */
+	C_STATE_C7_LONG_LAT,	/* 6 */
+	C_STATE_C7S_SHORT_LAT,	/* 7 */
+	C_STATE_C7S_LONG_LAT,	/* 8 */
+	C_STATE_C8,		/* 9 */
+	C_STATE_C9,		/* 10 */
+	C_STATE_C10,		/* 11 */
+	NUM_C_STATES
+};
+
+#define MWAIT_RES(state, sub_state)				\
+	{							\
+		.addrl = (((state) << 4) | (sub_state)),	\
+		.space_id = ACPI_ADDRESS_SPACE_FIXED,		\
+		.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,	\
+		.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,	\
+		.access_size = ACPI_FFIXEDHW_FLAG_HW_COORD,	\
+	}
+
+static const acpi_cstate_t cstate_map[NUM_C_STATES] = {
+	[C_STATE_C0] = {},
+	[C_STATE_C1] = {
+		.latency = 0,
+		.power = C1_POWER,
+		.resource = MWAIT_RES(0, 0),
+	},
+	[C_STATE_C1E] = {
+		.latency = 0,
+		.power = C1_POWER,
+		.resource = MWAIT_RES(0, 1),
+	},
+	[C_STATE_C6_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C6_POWER,
+		.resource = MWAIT_RES(2, 0),
+	},
+	[C_STATE_C6_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C6_POWER,
+		.resource = MWAIT_RES(2, 1),
+	},
+	[C_STATE_C7_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C7_POWER,
+		.resource = MWAIT_RES(3, 0),
+	},
+	[C_STATE_C7_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C7_POWER,
+		.resource = MWAIT_RES(3, 1),
+	},
+	[C_STATE_C7S_SHORT_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C7_POWER,
+		.resource = MWAIT_RES(3, 2),
+	},
+	[C_STATE_C7S_LONG_LAT] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C7_POWER,
+		.resource = MWAIT_RES(3, 3),
+	},
+	[C_STATE_C8] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C8_POWER,
+		.resource = MWAIT_RES(4, 0),
+	},
+	[C_STATE_C9] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C9_POWER,
+		.resource = MWAIT_RES(5, 0),
+	},
+	[C_STATE_C10] = {
+		.latency = C_STATE_LATENCY_FROM_LAT_REG(0),
+		.power = C10_POWER,
+		.resource = MWAIT_RES(6, 0),
+	},
+};
+
+static int cstate_set_non_s0ix[] = {
+	C_STATE_C1E,
+	C_STATE_C6_LONG_LAT,
+	C_STATE_C7S_LONG_LAT
+};
+
+static int cstate_set_s0ix[] = {
+	C_STATE_C1E,
+	C_STATE_C7S_LONG_LAT,
+	C_STATE_C10
+};
+
+acpi_cstate_t *soc_get_cstate_map(size_t *entries)
+{
+	static acpi_cstate_t map[MAX(ARRAY_SIZE(cstate_set_s0ix),
+				ARRAY_SIZE(cstate_set_non_s0ix))];
+	int *set;
+	int i;
+
+	config_t *config = config_of_soc();
+
+	int is_s0ix_enable = config->s0ix_enable;
+
+	if (is_s0ix_enable) {
+		*entries = ARRAY_SIZE(cstate_set_s0ix);
+		set = cstate_set_s0ix;
+	} else {
+		*entries = ARRAY_SIZE(cstate_set_non_s0ix);
+		set = cstate_set_non_s0ix;
+	}
+
+	for (i = 0; i < *entries; i++) {
+		memcpy(&map[i], &cstate_map[set[i]], sizeof(acpi_cstate_t));
+		map[i].ctype = i + 1;
+	}
+	return map;
+}
+
+void soc_power_states_generation(int core_id, int cores_per_package)
+{
+	config_t *config = config_of_soc();
+
+	if (config->eist_enable)
+		/* Generate P-state tables */
+		generate_p_state_entries(core_id, cores_per_package);
+}
+
+void soc_fill_fadt(acpi_fadt_t *fadt)
+{
+	const uint16_t pmbase = ACPI_BASE_ADDRESS;
+
+	config_t *config = config_of_soc();
+
+	fadt->pm_tmr_blk = pmbase + PM1_TMR;
+	fadt->pm_tmr_len = 4;
+	fadt->x_pm_tmr_blk.space_id = 1;
+	fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8;
+	fadt->x_pm_tmr_blk.bit_offset = 0;
+	fadt->x_pm_tmr_blk.access_size = 0;
+	fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR;
+	fadt->x_pm_tmr_blk.addrh = 0x0;
+
+	if (config->s0ix_enable)
+		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
+}
+
+uint32_t soc_read_sci_irq_select(void)
+{
+	uintptr_t pmc_bar = soc_read_pmc_base();
+	return read32((void *)pmc_bar + IRQ_REG);
+}
+
+static unsigned long soc_fill_dmar(unsigned long current)
+{
+	const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
+	uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
+	bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
+
+	if (igfx_dev && igfx_dev->enabled && gfxvtbar && gfxvten) {
+		unsigned long tmp = current;
+
+		current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
+		current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
+	uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
+	bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
+
+	if (ipu_dev && ipu_dev->enabled && ipuvtbar && ipuvten) {
+		unsigned long tmp = current;
+
+		current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
+		current += acpi_create_dmar_ds_pci(current, 0, 5, 0);
+
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	uint64_t vtvc0bar = MCHBAR64(VTVC0BAR) & VTBAR_MASK;
+	bool vtvc0en = MCHBAR32(VTVC0BAR) & VTBAR_ENABLED;
+
+	if (vtvc0bar && vtvc0en) {
+		const unsigned long tmp = current;
+
+		current += acpi_create_dmar_drhd(current,
+				DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+		current += acpi_create_dmar_ds_ioapic(current,
+				2, V_P2SB_CFG_IBDF_BUS, V_P2SB_CFG_IBDF_DEV,
+				V_P2SB_CFG_IBDF_FUNC);
+		current += acpi_create_dmar_ds_msi_hpet(current,
+				0, V_P2SB_CFG_HBDF_BUS, V_P2SB_CFG_HBDF_DEV,
+				V_P2SB_CFG_HBDF_FUNC);
+
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	/* TCSS Thunderbolt root ports */
+	for (unsigned int i = 0; i < MAX_TBT_PCIE_PORT; i++) {
+		uint64_t tbtbar = MCHBAR64(TBT0BAR + i * 8) & VTBAR_MASK;
+		bool tbten = MCHBAR32(TBT0BAR + i * 8) & VTBAR_ENABLED;
+		if (tbtbar && tbten) {
+			unsigned long tmp = current;
+
+			current += acpi_create_dmar_drhd(current, 0, 0, tbtbar);
+			current += acpi_create_dmar_ds_pci(current, 0, 7, i);
+
+			acpi_dmar_drhd_fixup(tmp, current);
+		}
+	}
+
+	/* Add RMRR entry */
+	const unsigned long tmp = current;
+	current += acpi_create_dmar_rmrr(current, 0,
+		sa_get_gsm_base(), sa_get_tolud_base() - 1);
+	current += acpi_create_dmar_ds_pci(current, 0, 2, 0);
+	acpi_dmar_rmrr_fixup(tmp, current);
+
+	return current;
+}
+
+unsigned long sa_write_acpi_tables(struct device *dev, unsigned long current,
+				   struct acpi_rsdp *rsdp)
+{
+	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+
+	/*
+	 * Create DMAR table only if we have VT-d capability and FSP does not override its
+	 * feature.
+	 */
+	if ((pci_read_config32(dev, CAPID0_A) & VTD_DISABLE) ||
+	    !(MCHBAR32(VTVC0BAR) & VTBAR_ENABLED))
+		return current;
+
+	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP | DMA_CTRL_PLATFORM_OPT_IN_FLAG, soc_fill_dmar);
+	current += dmar->header.length;
+	current = acpi_align_current(current);
+	acpi_add_table(rsdp, dmar);
+
+	return current;
+}
+
+void acpi_create_gnvs(struct global_nvs_t *gnvs)
+{
+	config_t *config = config_of_soc();
+
+	/* Set unknown wake source */
+	gnvs->pm1i = -1;
+
+	/* CPU core count */
+	gnvs->pcnt = dev_count_cpu();
+
+	if (CONFIG(CONSOLE_CBMEM))
+		/* Update the mem console pointer. */
+		gnvs->cbmc = (uintptr_t)cbmem_find(CBMEM_ID_CONSOLE);
+
+	if (CONFIG(CHROMEOS)) {
+		/* Initialize Verified Boot data */
+		chromeos_init_chromeos_acpi(&(gnvs->chromeos));
+		if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+			gnvs->chromeos.vbt2 = google_ec_running_ro() ?
+				ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
+		} else
+			gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO;
+	}
+
+	/* Enable DPTF based on mainboard configuration */
+	gnvs->dpte = config->dptf_enable;
+
+	/* Fill in the Wifi Region id */
+	gnvs->cid1 = wifi_regulatory_domain();
+
+	/* Set USB2/USB3 wake enable bitmaps. */
+	gnvs->u2we = config->usb2_wake_enable_bitmap;
+	gnvs->u3we = config->usb3_wake_enable_bitmap;
+
+	/* Fill in Above 4GB MMIO resource */
+	sa_fill_gnvs(gnvs);
+}
+
+uint32_t acpi_fill_soc_wake(uint32_t generic_pm1_en,
+			    const struct chipset_power_state *ps)
+{
+	/*
+	 * WAK_STS bit is set when the system is in one of the sleep states
+	 * (via the SLP_EN bit) and an enabled wake event occurs. Upon setting
+	 * this bit, the PMC will transition the system to the ON state and
+	 * can only be set by hardware and can only be cleared by writing a one
+	 * to this bit position.
+	 */
+
+	generic_pm1_en |= WAK_STS | RTC_EN | PWRBTN_EN;
+	return generic_pm1_en;
+}
+
+int soc_madt_sci_irq_polarity(int sci)
+{
+	return MP_IRQ_POLARITY_HIGH;
+}