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authorShreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>2020-12-03 14:07:15 -0800
committerFurquan Shaikh <furquan@google.com>2020-12-14 23:05:25 +0000
commit87c7ec7c0677ec5fda4a9cebb95c06edb23a96ba (patch)
tree0851933ccc52497f866c0aebaff15871db8375c6 /src/soc/intel/jasperlake/Kconfig
parent5f7343273708490137163445c4a3ba38ed2b7b1e (diff)
soc/intel: Remove INTEL_CAR_NEM_ENHANCED_V2 config option
SF Mask MSRs' Programming which was done under this config selection will be moved under a new config option called CAR_HAS_SF_MASKS. This segregates the eNEM programming sequence based on sub features supported in each processor. Bug=b:171601324 BRANCH=volteer Test=Build volteer build and boot on Delbin EVT. Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/jasperlake/Kconfig')
-rw-r--r--src/soc/intel/jasperlake/Kconfig2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 294f19f87b..0a15f052d9 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -23,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE
+ select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT if RUN_FSP_GOP
select IOAPIC
@@ -61,7 +62,6 @@ config CPU_SPECIFIC_OPTIONS
select TSC_MONOTONIC_TIMER
select UDELAY_TSC
select UDK_202005_BINDING
- select USE_CAR_NEM_ENHANCED_V1
select DISPLAY_FSP_VERSION_INFO
select HECI_DISABLE_USING_SMM