diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-02-10 12:38:02 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 20:21:45 +0000 |
| commit | 34f26b298961300fe97234ac5f424f57ebd04aad (patch) | |
| tree | 9221a4e220dfacee5ecda62ee216104416933e74 /src/soc/intel/jasperlake/Kconfig | |
| parent | 03c0853f4d58c73a632f81cac2eb16b759d7f338 (diff) | |
drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove
"SKIP_" prefix.
1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM ->
USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT ->
USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE ->
USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
The idea here is to let SoC selects all required FSP configs to execute
FSP Notify Phase APIs unless SoC deselects those configs to run native
coreboot implementation as part of the `.final` ops.
For now all SoC that uses FSP APIs have selected all required configs
to let FSP to execute Notify Phase APIs.
Note: coreboot native implementation to skip FSP notify phase API (post
pci enumeration) is still WIP.
Additionally, fixed SoC configs inclusion order alphabetically.
BUG=b:211954778
TEST=Able to build and boot brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/jasperlake/Kconfig')
| -rw-r--r-- | src/soc/intel/jasperlake/Kconfig | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 8fb0f49506..48b735e8d1 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -15,6 +15,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select COS_MAPPED_TO_MSB + select DISPLAY_FSP_VERSION_INFO_2 select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 @@ -22,6 +23,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER + select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM_ENHANCED select INTEL_GMA_ACPI @@ -63,8 +65,9 @@ config CPU_SPECIFIC_OPTIONS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202005_BINDING - select DISPLAY_FSP_VERSION_INFO_2 - select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT + select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM + select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT + select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE config DCACHE_RAM_BASE default 0xfef00000 |