diff options
author | Michael Niewöhner <foss@mniewoehner.de> | 2019-10-19 15:17:06 +0200 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2019-11-04 19:24:49 +0000 |
commit | e75a64f822931a5fbdd80f20c4d168a5c346e01a (patch) | |
tree | be951bed3220dac1d7a9fc34c8e534da53f55311 /src/soc/intel/icelake | |
parent | 68da45479fd289281017768a8cfa51b2f642ac07 (diff) |
soc/intel: skl,cnl,icl: consolidate ebda and memmap
As of CB:36136 ebda and memmap are identical for skl, cnl and icl, thus
move them to common code.
Tested successfully on X11SSM-F
Change-Id: I9a20c814d2a6874fcb4ff99ef1a7825d891f74e2
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36137
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake')
-rw-r--r-- | src/soc/intel/icelake/Makefile.inc | 5 | ||||
-rw-r--r-- | src/soc/intel/icelake/memmap.c | 105 |
2 files changed, 0 insertions, 110 deletions
diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index a4ebd20580..67a3a7114a 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -21,12 +21,10 @@ bootblock-y += bootblock/pch.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c bootblock-y += gpio.c -bootblock-y += memmap.c bootblock-y += p2sb.c romstage-y += espi.c romstage-y += gpio.c -romstage-y += memmap.c romstage-y += reset.c ramstage-y += acpi.c @@ -39,7 +37,6 @@ ramstage-y += fsp_params.c ramstage-y += gpio.c ramstage-y += graphics.c ramstage-y += lockdown.c -ramstage-y += memmap.c ramstage-y += p2sb.c ramstage-y += pmc.c ramstage-y += reset.c @@ -54,8 +51,6 @@ smm-y += pmutil.c smm-y += smihandler.c smm-y += uart.c -postcar-y += memmap.c - CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake/include diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c deleted file mode 100644 index a4fd2e8a48..0000000000 --- a/src/soc/intel/icelake/memmap.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2018 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/romstage.h> -#include <cbmem.h> -#include <fsp/util.h> -#include <intelblocks/ebda.h> -#include <intelblocks/systemagent.h> -#include <stdlib.h> - -/* - * Fill up memory layout information - * - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | PRM (C6DRAM/SGX) | - * +--------------------------+ PRMRR - * | ME Stolen Memory | - * +--------------------------+ ME Stolen - * | PTT | - * +--------------------------+ top_of_ram - * | Reserved - FSP/CBMEM | - * +--------------------------+ TOLUM - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ -void fill_soc_memmap_ebda(struct ebda_config *cfg) -{ - struct range_entry tolum; - - fsp_find_bootloader_tolum(&tolum); - cfg->cbmem_top = range_entry_end(&tolum); -} - -void cbmem_top_init(void) -{ - /* Fill up EBDA area */ - fill_ebda_area(); -} - -/* - * +-------------------------+ Top of RAM (aligned) - * | System Management Mode | - * | code and data | Length: CONFIG_TSEG_SIZE - * | (TSEG) | - * +-------------------------+ SMM base (aligned) - * | | - * | Chipset Reserved Memory | - * | | - * +-------------------------+ top_of_ram (aligned) - * | | - * | CBMEM Root | - * | | - * +-------------------------+ - * | | - * | FSP Reserved Memory | - * | | - * +-------------------------+ - * | | - * | Various CBMEM Entries | - * | | - * +-------------------------+ top_of_stack (8 byte aligned) - * | | - * | stack (CBMEM Entry) | - * | | - * +-------------------------+ - */ -void *cbmem_top_chipset(void) -{ - struct ebda_config ebda_cfg; - - retrieve_ebda_object(&ebda_cfg); - - return (void *)(uintptr_t)ebda_cfg.cbmem_top; -} |