diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-07-08 14:49:22 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-07-11 05:57:41 +0000 |
| commit | 10a9432cc2ad77234442bd639194c5a80050854e (patch) | |
| tree | ce6f68feab9582d2ab62765cd0d9a3262bb62b69 /src/soc/intel/icelake | |
| parent | 5b9948140f97eceb47ba026d7bad6dfa2a3c483d (diff) | |
soc/intel/common/timer: Move USE_LEGACY_8254_TIMER into common/block/timer
This patch moves USE_LEGACY_8254_TIMER Kconfig into common/block/timer
for better code sharing. Also ported CB:33512 for SPT and ICP PCH.
Change-Id: Ic767ff97aaa3eb7fa35ffa38fa416d006eaa6e78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/icelake/espi.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/icelake/fsp_params.c | 4 |
3 files changed, 4 insertions, 13 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index 028f6b2c31..72596c46e2 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -204,8 +204,6 @@ struct soc_intel_icelake_config { /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ uint8_t eist_enable; - /* Statically clock gate 8254 PIT. */ - uint8_t clock_gate_8254; /* Enable C6 DRAM */ uint8_t enable_c6dram; /* diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index a4b6d80aa9..a98821c903 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -199,16 +199,6 @@ static void pch_misc_init(void) outb((1 << 7), 0x70); }; -static void clock_gate_8254(const struct device *dev) -{ - const config_t *config = dev->chip_info; - - if (!config->clock_gate_8254) - return; - - itss_clock_gate_8254(); -} - void lpc_soc_init(struct device *dev) { /* Legacy initialization */ @@ -229,7 +219,6 @@ void lpc_soc_init(struct device *dev) soc_pch_pirq_init(dev); setup_i8259(); i8259_configure_irq_trigger(9, 1); - clock_gate_8254(dev); soc_mirror_dmi_pcr_io_dec(); } diff --git a/src/soc/intel/icelake/fsp_params.c b/src/soc/intel/icelake/fsp_params.c index 8b65a89731..03b00d94fb 100644 --- a/src/soc/intel/icelake/fsp_params.c +++ b/src/soc/intel/icelake/fsp_params.c @@ -124,6 +124,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + /* Legacy 8254 timer support */ + params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER; + params->Enable8254ClockGatingOnS3 = 1; + /* S0ix */ params->PchPmSlpS0Enable = config->s0ix_enable; |