soc/intel/common: move common memmap functionality from skl,icl,cnl,apl

This moves common memmap functionality from skl,icl,cnl,apl to the common tree.

Change-Id: I45ddfabeac806ad5ff62da97ec1409c6bb9e89ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 0 insertions, 24 deletions

diff --git a/src/soc/intel/icelake/memmap.c b/src/soc/intel/icelake/memmap.c
index 00f45cf3ed..f17f255b13 100644
--- a/src/soc/intel/icelake/memmap.c
+++ b/src/soc/intel/icelake/memmap.c
@@ -29,12 +29,6 @@
 #include <soc/systemagent.h>
 #include <stdlib.h>
 
-void smm_region(uintptr_t *start, size_t *size)
-{
-	*start = sa_get_tseg_base();
-	*size = sa_get_tseg_size();
-}
-
 /* Calculate ME Stolen size */
 static size_t get_imr_size(void)
 {
@@ -240,21 +234,3 @@ void *cbmem_top(void)
 
 	return (void *)(uintptr_t)ebda_cfg.tolum_base;
 }
-
-void fill_postcar_frame(struct postcar_frame *pcf)
-{
-	uintptr_t top_of_ram;
-	/*
-	 * We need to make sure ramstage will be run cached. At this
-	 * point exact location of ramstage in cbmem is not known.
-	 * Instruct postcar to cache 16 megs under cbmem top which is
-	 * a safe bet to cover ramstage.
-	 */
-	top_of_ram = (uintptr_t) cbmem_top();
-	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
-	top_of_ram -= 16*MiB;
-	postcar_frame_add_mtrr(pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
-
-	/* Cache the TSEG region */
-	postcar_enable_tseg_cache(pcf);
-}