diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-29 17:26:58 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-10-26 06:51:53 +0000 |
| commit | 6f1754d090e79f6e4d06780a494b62a83a5d8fcc (patch) | |
| tree | f24a66023eb9382f7ff815d098c2af479be25f94 /src/soc/intel/icelake | |
| parent | a64b4f454894988a9c043d53d00b493852f261a3 (diff) | |
soc/intel/icl: enable common CPU code
Enable CPU_INTEL_COMMON to make common CPU code available to CNL, which
gets used in CB:45535 and CB:45536 for CPPC entries generation.
Note: This also retrieves the VMX Kconfig and enables it by default,
like done for SKL and CNL already.
Since FSP always set the feature config lock, SET_IA32_FC_LOCK_BIT gets
selected statically by the SoC to reflect this in menuconfig.
Change-Id: I58e86021687fc0a836324f70071f7ea80242b3cb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45826
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake')
| -rw-r--r-- | src/soc/intel/icelake/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 57367495ad..3b3d4793ee 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -11,6 +11,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ALL_STAGES_X86_32 select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS + select CPU_INTEL_COMMON + select SET_IA32_FC_LOCK_BIT select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select CPU_SUPPORTS_PM_TIMER_EMULATION select FSP_M_XIP |