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authorAngel Pons <th3fanbus@gmail.com>2022-08-10 20:38:06 +0200
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-08-12 17:10:30 +0000
commit0e7cf3d81d121181a94b6a594b944628c2e5a939 (patch)
tree8baa2abc2b6ae9d52c7b958fab3fdc510bc567db /src/soc/intel/icelake/systemagent.c
parenta8cf2f2d736172b7c7e88624f1439886ced5ecf4 (diff)
soc/intel/alderlake: Fix DDR5 channel mapping
DDR5 memory modules have two separate 32-bit channels (40-bit on ECC memory modules), and the SPD info refers to one channel: the primary bus width is 32 (or 40) bits and the "DIMM size" is halved. On Alder Lake, there are 2 memory controllers with 4 32-bit channels each for DDR5. FSP has 16 positions to store SPD data, some of which are only used with LPDDR4/LPDDR5. To try to make things less confusing, FSP abstracts the DDR5 channels so that the configuration works like on DDR4. This is done by copying each DIMM's SPD data to the other half-channel. Thus, fix the wrapper parameters for DDR5 accordingly. Tested on AlderLake-P DDR5 RVP (board ID 0x12), both DIMM slots now function properly. Without this patch, only the top slot would work. Change-Id: I5f01cd77388b89ba34d91c2dc5fb843fe9db9826 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Tested-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66608 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/icelake/systemagent.c')
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