soc/intel/icelake: Do initial SoC commit

Clone entirely from Cannonlake
commit id: 3487095304dbbbf66de86f8bce0e40b7acb3ea27

List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
   5.a. All NHLT blobs and related files.
   5.b. remove cnl_memcfg_init.c file, will be added later.
   5.c. Remove vr_config.c, this is WIP.
   5.d. Clean up upd override in fsp_params.c,
	will be added once FSP available.
   5.e Remove CNL-H based GPIO configuartion.

Ice Lake specific changes will follow in subsequent patches.

Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 148 insertions, 0 deletions

diff --git a/src/soc/intel/icelake/romstage/romstage.c b/src/soc/intel/icelake/romstage/romstage.c
new file mode 100644
index 0000000000..432cae5f33
--- /dev/null
+++ b/src/soc/intel/icelake/romstage/romstage.c
@@ -0,0 +1,148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <arch/early_variables.h>
+#include <assert.h>
+#include <chip.h>
+#include <cpu/x86/mtrr.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <fsp/util.h>
+#include <intelblocks/chip.h>
+#include <intelblocks/cse.h>
+#include <intelblocks/pmclib.h>
+#include <memory_info.h>
+#include <soc/intel/common/smbios.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
+#include <soc/romstage.h>
+#include <string.h>
+#include <timestamp.h>
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+#define FSP_SMBIOS_MEMORY_INFO_GUID	\
+{	\
+	0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e,	\
+	0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23	\
+}
+
+/* Save the DIMM information for SMBIOS table 17 */
+static void save_dimm_info(void)
+{
+	int channel, dimm, dimm_max, index;
+	size_t hob_size;
+	const CONTROLLER_INFO *ctrlr_info;
+	const CHANNEL_INFO *channel_info;
+	const DIMM_INFO *src_dimm;
+	struct dimm_info *dest_dimm;
+	struct memory_info *mem_info;
+	const MEMORY_INFO_DATA_HOB *memory_info_hob;
+	const uint8_t smbios_memory_info_guid[16] =
+			FSP_SMBIOS_MEMORY_INFO_GUID;
+
+	/* Locate the memory info HOB, presence validated by raminit */
+	memory_info_hob = fsp_find_extension_hob_by_guid(
+						smbios_memory_info_guid,
+						&hob_size);
+	if (memory_info_hob == NULL || hob_size == 0) {
+		printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n");
+		return;
+	}
+
+	/*
+	 * Allocate CBMEM area for DIMM information used to populate SMBIOS
+	 * table 17
+	 */
+	mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info));
+	if (mem_info == NULL) {
+		printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n");
+		return;
+	}
+	memset(mem_info, 0, sizeof(*mem_info));
+
+	/* Describe the first N DIMMs in the system */
+	index = 0;
+	dimm_max = ARRAY_SIZE(mem_info->dimm);
+	ctrlr_info = &memory_info_hob->Controller[0];
+	for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) {
+		channel_info = &ctrlr_info->ChannelInfo[channel];
+		if (channel_info->Status != CHANNEL_PRESENT)
+			continue;
+		for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) {
+			src_dimm = &channel_info->DimmInfo[dimm];
+			dest_dimm = &mem_info->dimm[index];
+
+			if (src_dimm->Status != DIMM_PRESENT)
+				continue;
+
+			/* Populate the DIMM information */
+			dimm_info_fill(dest_dimm,
+				src_dimm->DimmCapacity,
+				memory_info_hob->MemoryType,
+				memory_info_hob->ConfiguredMemoryClockSpeed,
+				channel_info->ChannelId,
+				src_dimm->DimmId,
+				(const char *)src_dimm->ModulePartNum,
+				sizeof(src_dimm->ModulePartNum),
+				memory_info_hob->DataWidth);
+			index++;
+		}
+	}
+	mem_info->dimm_cnt = index;
+	printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt);
+}
+
+asmlinkage void car_stage_entry(void)
+{
+	bool s3wake;
+	struct postcar_frame pcf;
+	uintptr_t top_of_ram;
+	struct chipset_power_state *ps = car_get_var_ptr(&power_state);
+
+	console_init();
+
+	/* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */
+	systemagent_early_init();
+	/* initialize Heci interface */
+	heci_init(HECI1_BASE_ADDRESS);
+
+	timestamp_add_now(TS_START_ROMSTAGE);
+	s3wake = pmc_fill_power_state(ps) == ACPI_S3;
+	fsp_memory_init(s3wake);
+	pmc_set_disb();
+	if (!s3wake)
+		save_dimm_info();
+	if (postcar_frame_init(&pcf, 1 * KiB))
+		die("Unable to initialize postcar frame.\n");
+
+	/*
+	 * We need to make sure ramstage will be run cached. At this
+	 * point exact location of ramstage in cbmem is not known.
+	 * Instruct postcar to cache 16 megs under cbmem top which is
+	 * a safe bet to cover ramstage.
+	 */
+	top_of_ram = (uintptr_t) cbmem_top();
+	printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram);
+	top_of_ram -= 16*MiB;
+	postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
+
+	/* Cache the ROM as WP just below 4GiB. */
+	postcar_frame_add_romcache(&pcf, MTRR_TYPE_WRPROT);
+
+	run_postcar_phase(&pcf);
+}