diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-04-29 12:37:27 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-05-02 06:02:40 +0000 |
| commit | ff9104eae3512e554b4790b40b0bdd3fca2036b3 (patch) | |
| tree | b5f1fd9a80151dab0150bcd2d395a858dd529fe2 /src/soc/intel/icelake/pmutil.c | |
| parent | d32a4930910dbe5dea47777902fcb966a4854114 (diff) | |
soc/intel/icelake: Clear PMCON status bits
This patch ports CB:31902 changes from CNL to ICL.
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/pmutil.c')
| -rw-r--r-- | src/soc/intel/icelake/pmutil.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index 96ff52d122..e1b1665368 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -141,6 +141,20 @@ void pmc_set_disb(void) write8(addr, disb_val); } +void pmc_clear_pmcon_sts(void) +{ + uint32_t reg_val; + uint8_t *addr; + addr = pmc_mmio_regs(); + + reg_val = read32(addr + GEN_PMCON_A); + /* Clear SUS_PWR_FLR, GBL_RST_STS, HOST_RST_STS, PWR_FLR bits + * while retaining MS4V write-1-to-clear bit */ + reg_val &= ~(MS4V); + + write32((addr + GEN_PMCON_A), reg_val); +} + /* * PMC controller gets hidden from PCI bus * during FSP-Silicon init call. Hence PWRMBASE |