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| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-07-01 00:13:29 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-12-10 12:07:43 +0000 |
| commit | df47e1c3e590c4aeb2e1dcd32dca194f91327e3f (patch) | |
| tree | eee5a8b17496782aa8e70ea11ca8cb67711b842e /src/soc/intel/icelake/memmap.c | |
| parent | 2b35780a277bd48bb2133a59ac920b3e03658c4e (diff) | |
mb/intel/icelake_rvp: Fill Icelake U and Y RVP devicetree parameters
This implementation configures below parameters:
1. Enable SaGv, isclk.
2. Set Pcie rootport enable, Clock source usage and clkreq.
3. Configure SATA and LPSS controllers parameters.
4. Enable CNVI controller, configure Wifi end device under PCIE RP1.
5. Add TPM device support under GSPI1.
Change-Id: I585e82799eea0bad19ad2c94d6b4b3024f930ed4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/30015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/memmap.c')
0 files changed, 0 insertions, 0 deletions