diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-01 21:26:42 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-11 20:49:53 +0000 |
| commit | 8a6c34e8ba9862814e53ad4f9b04ae1f2b9d4b49 (patch) | |
| tree | b4edf89d40b02f27ba4da19d04fa2217e2d5a1de /src/soc/intel/icelake/include | |
| parent | 11fae4ffe019ad648e517115aa1ec7bedbf4f648 (diff) | |
soc/intel/{icl,tgl,jsl,ehl}: add LPIT support
Add SLP_S0 residency register and enable LPIT support.
Change-Id: Id1abbe8dcb7796eeb26ccb72f1f26cf7a040dba4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49048
Reviewed-by: Lance Zhao
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/include')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/pmc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/include/soc/pmc.h b/src/soc/intel/icelake/include/soc/pmc.h index 26dae7e58d..2ca3328392 100644 --- a/src/soc/intel/icelake/include/soc/pmc.h +++ b/src/soc/intel/icelake/include/soc/pmc.h @@ -119,6 +119,8 @@ #define GBLRST_CAUSE0_THERMTRIP (1 << 5) #define GBLRST_CAUSE1 0x1928 +#define SLP_S0_RES 0x193c + #define CPPMVRIC 0x1B1C #define XTALSDQDIS (1 << 22) |