diff options
| author | Patrick Rudolph <patrick.rudolph@9elements.com> | 2020-05-12 16:04:47 +0200 |
|---|---|---|
| committer | Patrick Rudolph <siro@das-labor.org> | 2020-05-28 06:26:53 +0000 |
| commit | bf72dcbd2f1b0138a329f0c9adac33c387e8cd9f (patch) | |
| tree | f20fbe8e0f8a5896bf367bb02f91b869912ccbd9 /src/soc/intel/icelake/include | |
| parent | 78e8db1eebaf4e90c0de2b38a0cc8832057766a7 (diff) | |
soc/intel/common: Improve Type16 SMBIOS tables
Use CAPID0_A to provide information closer to reality.
* Correctly advertise ECC support, max DIMM count and max capacity
* CAPID0_A hasn't changed since SNB, but most EDS mark the bits as
reserved even though they are still used by FSP.
* Assume the same bits for Tiger Lake as for Ice Lake
* Assume the same bits for Skylake as for Coffee Lake
* Add CAPID0_A to Icelake headers
The lastest complete documentation can be found in Document: 341078-002.
Change-Id: I0d8fbb512fccbd99a6cfdacadc496d8266ae4cc7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Diffstat (limited to 'src/soc/intel/icelake/include')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/systemagent.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 297ee5d56c..90465a248b 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -15,6 +15,7 @@ #define D_LCK (1 << 4) #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 #define EDRAMBAR 0x5408 |