diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-04-29 13:28:11 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-05-02 06:02:52 +0000 |
| commit | 5489341e6380cb8c7d1249a495486ae9cfcd4fa2 (patch) | |
| tree | a33e36b2b46d4a0d6addf9503a607d1e3cafad59 /src/soc/intel/icelake/include | |
| parent | ff9104eae3512e554b4790b40b0bdd3fca2036b3 (diff) | |
soc/intel/icelake: Add chipset event logging
This patch ports CB:30718 and CB:31908 changes from CNL to ICL.
Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.
Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/include')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/pch.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/include/soc/pch.h b/src/soc/intel/icelake/include/soc/pch.h index d5478d26e9..e1560c1657 100644 --- a/src/soc/intel/icelake/include/soc/pch.h +++ b/src/soc/intel/icelake/include/soc/pch.h @@ -26,6 +26,4 @@ #define PCIE_CLK_LAN 0x70 #define PCIE_CLK_FREE 0x80 -void pch_log_state(void); - #endif |