diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2020-07-30 12:26:10 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-08-09 11:03:37 +0000 |
| commit | 8aa86c9c1b630d4a3b635ccedf0e144b217597f9 (patch) | |
| tree | 94ae971edaf4184c21a81f0401ad3d92f144d5cd /src/soc/intel/icelake/include | |
| parent | e4b22e7f19c7a2ed0d7b0126eb630c3c57af6003 (diff) | |
soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL.
Removing the register programming for these platforms. The write to
this register does not take effect and remains configured to 0, even
when programmed.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I3f581b90ea99012980f439a7914e8d901585b004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/soc/intel/icelake/include')
| -rw-r--r-- | src/soc/intel/icelake/include/soc/systemagent.h | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 90465a248b..ef648a66b3 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 |