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authorFelix Held <felix-coreboot@felixheld.de>2021-07-12 23:46:21 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-07-14 02:19:51 +0000
commitceb2fbb9203c66478f1566d7fcfebc5d807bdb32 (patch)
tree8137e9eb19d88e682a8d59ab5640c60f48861a14 /src/soc/intel/icelake/elog.c
parent78ab06ace918f6efa1a36c896b85806c5f617393 (diff)
include/cpu/x86/msr: add IA32_ prefix to MC0_ADDR and MC0_MISC
Those registers are architectural MSR and this also gets them in line with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are ascending. Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/elog.c')
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