summaryrefslogtreecommitdiff
path: root/src/soc/intel/icelake/chip.h
diff options
context:
space:
mode:
authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:42:14 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:15:25 +0000
commit2854f40668f37c09c5afa5e7ac670adfaacb44b4 (patch)
tree2c518c284f486a4c68b2babe10d55779c61cc7d5 /src/soc/intel/icelake/chip.h
parentee65079c9657f8e1f8ac1ea3d562b531368eecb7 (diff)
src/soc/intel: Drop unneeded empty lines
Change-Id: Id93aab5630e928ee4d7e957801e15a4cc8739fae Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/chip.h')
-rw-r--r--src/soc/intel/icelake/chip.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index d60791bb28..386e77520a 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -82,7 +82,6 @@ struct soc_intel_icelake_config {
SaGv_Enabled,
} SaGv;
-
/* Rank Margin Tool. 1:Enable, 0:Disable */
uint8_t RMT;