diff options
| author | Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> | 2020-05-08 21:01:31 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-20 09:13:55 +0000 |
| commit | 425d8640fa3d8e4a43bd9f2cc8f8fd7fedf675c3 (patch) | |
| tree | e87a20b6b5a98790b19f3c0bc49fffa76777abff /src/soc/intel/icelake/chip.h | |
| parent | b7911c8e98f493d29acedaf1542f98ad76700f00 (diff) | |
icelake: remove unused processor power limits configuration
Remove unused processor power limit configuration parameter
and function call based on common code base support for
Intel Icelake SoC based platform.
BRANCH=None
BUG=None
TEST=Built for icelake based dragonegg board.
Change-Id: Id8923f2c176092b6f7acfbfb079587f88258dce8
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41236
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/chip.h')
| -rw-r--r-- | src/soc/intel/icelake/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h index d67a70c3dc..2b190cd5df 100644 --- a/src/soc/intel/icelake/chip.h +++ b/src/soc/intel/icelake/chip.h @@ -171,8 +171,6 @@ struct soc_intel_icelake_config { /* HeciEnabled decides the state of Heci1 at end of boot * Setting to 0 (default) disables Heci1 and hides the device from OS */ uint8_t HeciEnabled; - /* PL2 Override value in Watts */ - uint32_t tdp_pl2_override; /* Intel Speed Shift Technology */ uint8_t speed_shift_enable; /* Enable VR specific mailbox command |