diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-10-31 23:08:14 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-06-13 04:38:08 +0000 |
| commit | 3d152ac388fa43b4c3d1bfeedcb6a40f1479ace3 (patch) | |
| tree | ca39c17047de8a3059cea7314f95910f2b45a8a1 /src/soc/intel/icelake/bootblock | |
| parent | 8a70918b8a78d8d5cd27e830cc4ae496b10d4f32 (diff) | |
soc/intel/icelake: Replace PCI device LPC to ESPI as per EDS
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Diffstat (limited to 'src/soc/intel/icelake/bootblock')
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 6 | ||||
| -rw-r--r-- | src/soc/intel/icelake/bootblock/report_platform.c | 24 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 094079140d..aefcaa5a47 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -26,8 +26,8 @@ #include <intelblocks/smbus.h> #include <intelblocks/tco.h> #include <soc/bootblock.h> +#include <soc/espi.h> #include <soc/iomap.h> -#include <soc/lpc.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> @@ -145,8 +145,8 @@ void pch_early_iorange_init(void) if (pch_check_decode_enable() == 0) { io_enables = lpc_enable_fixed_io_ranges(io_enables); /* - * Set up LPC IO Enables PCR[DMI] + 2774h [15:0] to the same - * value program in LPC PCI offset 82h. + * Set up ESPI IO Enables PCR[DMI] + 2774h [15:0] to the same + * value program in ESPI PCI offset 82h. */ pcr_write16(PID_DMI, PCR_DMI_LPCIOE, io_enables); } diff --git a/src/soc/intel/icelake/bootblock/report_platform.c b/src/soc/intel/icelake/bootblock/report_platform.c index e7c010e4d2..a9eef40756 100644 --- a/src/soc/intel/icelake/bootblock/report_platform.c +++ b/src/soc/intel/icelake/bootblock/report_platform.c @@ -46,16 +46,16 @@ static struct { }; static struct { - u16 lpcid; + u16 espiid; const char *name; } pch_table[] = { - { PCI_DEVICE_ID_INTEL_ICL_BASE_U_LPC, "Icelake-U Base" }, - { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_LPC, "Icelake-Y Base" }, - { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_LPC, "Icelake-U Premium" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC, "Icelake-U Super" }, - { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_LPC_REV0, "Icelake-U Super REV0" }, - { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_LPC, "Icelake-Y Super" }, - { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_LPC, "Icelake-Y Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_U_ESPI, "Icelake-U Base" }, + { PCI_DEVICE_ID_INTEL_ICL_BASE_Y_ESPI, "Icelake-Y Base" }, + { PCI_DEVICE_ID_INTEL_ICL_U_PREMIUM_ESPI, "Icelake-U Premium" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI, "Icelake-U Super" }, + { PCI_DEVICE_ID_INTEL_ICL_U_SUPER_U_ESPI_REV0, "Icelake-U Super REV0" }, + { PCI_DEVICE_ID_INTEL_ICL_SUPER_Y_ESPI, "Icelake-Y Super" }, + { PCI_DEVICE_ID_INTEL_ICL_Y_PREMIUM_ESPI, "Icelake-Y Premium" }, }; static struct { @@ -170,18 +170,18 @@ static void report_mch_info(void) static void report_pch_info(void) { int i; - pci_devfn_t dev = PCH_DEV_LPC; - uint16_t lpcid = get_dev_id(dev); + pci_devfn_t dev = PCH_DEV_ESPI; + uint16_t espiid = get_dev_id(dev); const char *pch_type = "Unknown"; for (i = 0; i < ARRAY_SIZE(pch_table); i++) { - if (pch_table[i].lpcid == lpcid) { + if (pch_table[i].espiid == espiid) { pch_type = pch_table[i].name; break; } } printk(BIOS_DEBUG, "PCH: device id %04x (rev %02x) is %s\n", - lpcid, get_dev_revision(dev), pch_type); + espiid, get_dev_revision(dev), pch_type); } static void report_igd_info(void) |