diff options
| author | Aamir Bohra <aamir.bohra@intel.com> | 2018-06-30 12:38:43 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-11-05 04:18:13 +0000 |
| commit | c7267631e23ec113de898bf07b5f6f212acc3629 (patch) | |
| tree | dec3e0e3bd1ffb25b9b70d88659a2741283e014c /src/soc/intel/icelake/bootblock | |
| parent | 5c568e00a5ca72e70a752aeb521b23892811dc69 (diff) | |
soc/intel/icelake: Add PID based on Icelake EDS
Change-Id: I2d9e06f06a39dc76a3c1351d7976505d7bd92d10
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/soc/intel/icelake/bootblock')
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 33 |
1 files changed, 6 insertions, 27 deletions
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 2fc94f4820..96722e21be 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -34,9 +34,7 @@ #include <soc/pm.h> #include <soc/smbus.h> -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP 0x1400 -#define PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H 0x0980 - +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 @@ -56,20 +54,6 @@ #define PCR_DMI_LPCIOD 0x2770 #define PCR_DMI_LPCIOE 0x2774 -static uint32_t get_pmc_reg_base(void) -{ - uint8_t pch_series; - - pch_series = get_pch_series(); - - if (pch_series == PCH_H) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_H; - else if (pch_series == PCH_LP) - return PCR_PSF3_TO_SHDW_PMC_REG_BASE_CNP_LP; - else - return 0; -} - static void soc_config_pwrmbase(void) { uint32_t reg32; @@ -113,26 +97,21 @@ void bootblock_pch_early_init(void) static void soc_config_acpibase(void) { uint32_t pmc_reg_value; - uint32_t pmc_base_reg; - - pmc_base_reg = get_pmc_reg_base(); - if (!pmc_base_reg) - die("Invalid PMC base address\n"); - pmc_reg_value = pcr_read32(PID_PSF3, pmc_base_reg + - PCR_PSFX_TO_SHDW_BAR4); + pmc_reg_value = pcr_read32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + + PCR_PSFX_TO_SHDW_BAR4); if (pmc_reg_value != 0xFFFFFFFF) { /* Disable Io Space before changing the address */ - pcr_rmw32(PID_PSF3, pmc_base_reg + + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_T0_SHDW_PCIEN, ~PCR_PSFX_TO_SHDW_PCIEN_IOEN, 0); /* Program ABASE in PSF3 PMC space BAR4*/ - pcr_write32(PID_PSF3, pmc_base_reg + + pcr_write32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_TO_SHDW_BAR4, ACPI_BASE_ADDRESS); /* Enable IO Space */ - pcr_rmw32(PID_PSF3, pmc_base_reg + + pcr_rmw32(PID_PSF3, PCR_PSF3_TO_SHDW_PMC_REG_BASE + PCR_PSFX_T0_SHDW_PCIEN, ~0, PCR_PSFX_TO_SHDW_PCIEN_IOEN); } |