diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-11-05 16:54:58 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-07 14:14:11 +0000 |
| commit | 1b1a26acdc814d0478bb5fda0b6664076a60fdf1 (patch) | |
| tree | 50add962d32b07ff52ab40e166f2bf078fabd82f /src/soc/intel/icelake/bootblock | |
| parent | 114e2e88305a6e1fc972a58a03b89a23685e5a48 (diff) | |
soc/intel/icelake: Refactor pch_early_init() code
This patch keeps required pch_early_init() function like ABASE programming,
GPE and RTC init into bootblock and moves remaining functions like
TCO configuration and SMBUS init into romstage/pch.c in order to maintain
only required chipset programming for bootblock and verstage.
TEST=Able to build and boot ICL DE system.
Change-Id: I4f0914242c3215f6bf76e41c468f544361a740d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36627
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/icelake/bootblock')
| -rw-r--r-- | src/soc/intel/icelake/bootblock/pch.c | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index e95220b90e..b8a404b379 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2018-2019 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,17 +23,13 @@ #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> -#include <intelblocks/smbus.h> -#include <intelblocks/tco.h> #include <soc/bootblock.h> -#include <soc/espi.h> #include <soc/iomap.h> #include <soc/p2sb.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/pcr_ids.h> #include <soc/pm.h> -#include <soc/smbus.h> #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x0600 #define PCR_PSFX_TO_SHDW_BAR0 0 @@ -94,7 +90,6 @@ void bootblock_pch_early_init(void) soc_config_pwrmbase(); } - static void soc_config_acpibase(void) { uint32_t pmc_reg_value; @@ -163,12 +158,6 @@ void pch_early_init(void) */ soc_config_acpibase(); - /* Programming TCO_BASE_ADDRESS and TCO Timer Halt */ - tco_configure(); - - /* Program SMBUS_BASE_ADDRESS and Enable it */ - smbus_common_init(); - /* Set up GPE configuration */ pmc_gpe_init(); |