soc/intel/icelake: Do initial SoC commit

Clone entirely from Cannonlake
commit id: 3487095304dbbbf66de86f8bce0e40b7acb3ea27

List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
   5.a. All NHLT blobs and related files.
   5.b. remove cnl_memcfg_init.c file, will be added later.
   5.c. Remove vr_config.c, this is WIP.
   5.d. Clean up upd override in fsp_params.c,
	will be added once FSP available.
   5.e Remove CNL-H based GPIO configuartion.

Ice Lake specific changes will follow in subsequent patches.

Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 55 insertions, 0 deletions

diff --git a/src/soc/intel/icelake/acpi/globalnvs.asl b/src/soc/intel/icelake/acpi/globalnvs.asl
new file mode 100644
index 0000000000..678ce5ac23
--- /dev/null
+++ b/src/soc/intel/icelake/acpi/globalnvs.asl
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+/* Global Variables */
+
+Name (\PICM, 0)		// IOAPIC/8259
+
+/*
+ * Global ACPI memory region. This region is used for passing information
+ * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
+ * Since we don't know where this will end up in memory at ACPI compile time,
+ * we have to fix it up in coreboot's ACPI creation phase.
+ */
+
+External (NVSA)
+
+OperationRegion (GNVS, SystemMemory, NVSA, 0x2000)
+Field (GNVS, ByteAcc, NoLock, Preserve)
+{
+	/* Miscellaneous */
+	Offset (0x00),
+	OSYS,	16,	// 0x00 - Operating System
+	SMIF,	8,	// 0x02 - SMI function
+	PCNT,	8,	// 0x03 - Processor Count
+	PPCM,	8,	// 0x04 - Max PPC State
+	TLVL,	8,	// 0x05 - Throttle Level Limit
+	LIDS,	8,	// 0x06 - LID State
+	PWRS,	8,	// 0x07 - AC Power State
+	CBMC,	32,	// 0x08 - 0x0b AC Power State
+	PM1I,	64,	// 0x0c - 0x13 PM1 wake status bit
+	GPEI,	64,	// 0x14 - 0x17 GPE wake status bit
+	DPTE,	8,	// 0x1c - Enable DPTF
+	NHLA,	64,	// 0x1d - 0x24 NHLT Address
+	NHLL,	32,	// 0x25 - 0x28 NHLT Length
+	CID1,	16,	// 0x29 - 0x2a Wifi Country Identifier
+	U2WE,	16,	// 0x2b - 0x2c USB2 Wake Enable Bitmap
+	U3WE,	16,	// 0x2d - 0x2e USB3 Wake Enable Bitmap
+	UIOR,	8,	// 0x2f - UART debug controller init on S3 resume
+
+	/* ChromeOS specific */
+	Offset (0x100),
+	#include <vendorcode/google/chromeos/acpi/gnvs.asl>
+}