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authorPatrick Rudolph <siro@das-labor.org>2018-10-01 19:17:11 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-10-22 08:35:25 +0000
commit45022ae056cdbf58429b77daf2da176306312801 (patch)
tree4218666e3c14e41232778c4ceff301292b3c61d9 /src/soc/intel/fsp_broadwell_de
parent33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff)
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to perform a "system reset" in their hard_reset() implementation. Replace all duplicate CF9 reset implementations for these platforms. Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/28862 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de')
-rw-r--r--src/soc/intel/fsp_broadwell_de/Kconfig2
-rw-r--r--src/soc/intel/fsp_broadwell_de/Makefile.inc2
-rw-r--r--src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c4
-rw-r--r--src/soc/intel/fsp_broadwell_de/include/soc/reset.h24
-rw-r--r--src/soc/intel/fsp_broadwell_de/reset.c29
5 files changed, 3 insertions, 58 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig
index 26c40947a7..ec010b3882 100644
--- a/src/soc/intel/fsp_broadwell_de/Kconfig
+++ b/src/soc/intel/fsp_broadwell_de/Kconfig
@@ -12,7 +12,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
- select HAVE_HARD_RESET
+ select SOUTHBRIDGE_INTEL_COMMON_RESET
select NO_RELOCATABLE_RAMSTAGE
select PARALLEL_MP
select SMP
diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc
index 931266314c..544819088d 100644
--- a/src/soc/intel/fsp_broadwell_de/Makefile.inc
+++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc
@@ -23,8 +23,6 @@ ramstage-y += tsc_freq.c
romstage-y += memmap.c
ramstage-y += memmap.c
ramstage-y += southcluster.c
-romstage-y += reset.c
-ramstage-y += reset.c
ramstage-y += acpi.c
ramstage-y += smbus_common.c
ramstage-y += smbus.c
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
index 148ffdc367..800f68653b 100644
--- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -20,11 +20,11 @@
#include <bootstate.h>
#include <cbfs.h>
#include <cbmem.h>
+#include <cf9_reset.h>
#include <device/device.h>
#include <device/pci_def.h>
#include <drivers/intel/fsp1_0/fsp_util.h>
#include <soc/pci_devs.h>
-#include <soc/reset.h>
#include <soc/romstage.h>
#include <chip.h>
#include <fsp.h>
@@ -142,7 +142,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr)
*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
if (Status == 0xFFFFFFFF) {
- warm_reset();
+ system_reset();
}
romstage_main_continue(Status, HobListPtr);
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
deleted file mode 100644
index fa0ceac091..0000000000
--- a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _SOC_RESET_H_
-#define _SOC_RESET_H_
-
-#include <reset.h>
-
-void warm_reset(void);
-
-#endif /* _SOC_RESET_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/reset.c b/src/soc/intel/fsp_broadwell_de/reset.c
deleted file mode 100644
index 78d74939e3..0000000000
--- a/src/soc/intel/fsp_broadwell_de/reset.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015-2016 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <arch/io.h>
-#include <soc/reset.h>
-
-void warm_reset(void)
-{
- outb(0x00, 0xcf9);
- outb(0x06, 0xcf9);
-}
-
-void do_hard_reset(void)
-{
- warm_reset();
-}