diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2019-10-11 11:31:08 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-10-16 14:11:17 +0000 |
| commit | ee0b7ad683fabafef228c624348057d31fe1e6d2 (patch) | |
| tree | d7f29474b13e94f3e3f2a1745749a5725fed80f9 /src/soc/intel/fsp_broadwell_de/southcluster.c | |
| parent | 89f596764775f5de53d4e17a95d2ec88c254e24a (diff) | |
mainboard/ocp/monolake: Hide IIO root ports before memory init
It turned on some SKUs FSP hangs in Notify stage if IIO root ports are
disabled after MemoryInit. To address that hide IIO root ports earlier
in romstage.
TEST=the patch was ran on affected HW and success was reported
Change-Id: I6a2a405f729df14f46bcf34a24e66e8ba9415f9d
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/southcluster.c')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/southcluster.c | 23 |
1 files changed, 5 insertions, 18 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c index d1981fd75b..fb8af87b62 100644 --- a/src/soc/intel/fsp_broadwell_de/southcluster.c +++ b/src/soc/intel/fsp_broadwell_de/southcluster.c @@ -257,24 +257,11 @@ void southcluster_enable_dev(struct device *dev) const int slot = PCI_SLOT(dev->path.pci.devfn); const int func = PCI_FUNC(dev->path.pci.devfn); - switch (slot) { - case PCIE_IIO_PORT_0_DEV: - die("should not hide PCH link"); - case PCIE_IIO_PORT_1_DEV: /* fallthrough */ - case PCIE_IIO_PORT_2_DEV: /* fallthrough */ - case PCIE_IIO_PORT_3_DEV: /* fallthrough */ - printk(BIOS_DEBUG, "%s: Disabling IOU bridge %02x.%01x\n", dev_path(dev), slot, - func); - iio_hide(slot, func); - break; - default: - printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, - func); - /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); - } + printk(BIOS_DEBUG, "%s: Disabling device: %02x.%01x\n", dev_path(dev), slot, func); + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); } #if CONFIG(HAVE_ACPI_TABLES) |