diff options
| author | Andrey Petrov <anpetrov@fb.com> | 2019-08-01 15:09:37 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-08-14 03:35:52 +0000 |
| commit | 4a73bf8378d8e36f0bae1488aa0b17cb5d5bd4ce (patch) | |
| tree | 69b3e5f75efb4aef4a91260b9ce367fddc2c2ed2 /src/soc/intel/fsp_broadwell_de/romstage/romstage.c | |
| parent | 3f85edbcc554c4db704ed23bdfb1f384f5e2239e (diff) | |
soc/intel/fsp_broadwell_de: Populate SMBIOS tables with memory information
Add code to read SPD data, parse it and save into SMBIOS table. This is
implemented for socketed DDR4 chips only. For soldered-down memory this
is not implemented and probably won't be ever needed.
TEST=tested on OCP Monolake mainboard, and found dmidecode -t memory to
work. The stack has also been tested on an out-of-tree board.
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Change-Id: I1162eb4484dab46f1ab9fe3426eecc4d9378e8e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/romstage/romstage.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c index 085395e9a8..3b74a1cb69 100644 --- a/src/soc/intel/fsp_broadwell_de/romstage/romstage.c +++ b/src/soc/intel/fsp_broadwell_de/romstage/romstage.c @@ -29,6 +29,7 @@ #include <pc80/mc146818rtc.h> #include <soc/iomap.h> #include <soc/lpc.h> +#include <soc/memory.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/gpio.h> @@ -165,6 +166,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) die("Could not allocate cbmem for HOB pointer"); *(u32 *)cbmem_hob_ptr = (u32)hob_list_ptr; + if (!CONFIG(FSP_MEMORY_DOWN)) + save_dimm_info(); + /* Load the ramstage. */ post_code(0x4e); run_ramstage(); |