soc/intel: Add Broadwell-DE SoC support

Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.

Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>

11 files changed, 566 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h
new file mode 100644
index 0000000000..f717d15a3b
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/acpi.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ACPI_H_
+#define _SOC_ACPI_H_
+
+#include <arch/acpi.h>
+
+void acpi_create_intel_hpet(acpi_hpet_t *hpet);
+void acpi_fill_in_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt);
+unsigned long acpi_madt_irq_overrides(unsigned long current);
+uint16_t get_pmbase(void);
+
+#endif /* _SOC_ACPI_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
new file mode 100644
index 0000000000..6828d03dc9
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/broadwell_de.h
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_BROADWELL_DE_H_
+#define _SOC_BROADWELL_DE_H_
+
+#endif /* _SOC_BROADWELL_DE_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h
new file mode 100644
index 0000000000..ca842997a9
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/iomap.h
@@ -0,0 +1,66 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_IOMAP_H_
+#define _SOC_IOMAP_H_
+
+/*
+ * Memory Mapped IO bases.
+ */
+
+/* PCI Configuration Space */
+#define MCFG_BASE_ADDRESS        CONFIG_MMCONF_BASE_ADDRESS
+#define MCFG_BASE_SIZE           0x10000000
+
+/* Transactions in this range will abort */
+#define ABORT_BASE_ADDRESS       0xfeb00000
+#define ABORT_BASE_SIZE          0x00010000
+
+/* PSEG */
+#define PSEG_BASE_ADDRESS        0xfeb80000
+#define PSEG_BASE_SIZE           0x00080000
+
+/* IOxAPIC */
+#define IOXAPIC1_BASE_ADDRESS    0xfec00000
+#define IOXAPIC1_BASE_SIZE       0x00100000
+#define IOXAPIC2_BASE_ADDRESS    0xfec01000
+#define IOXAPIC2_BASE_SIZE       0x00100000
+
+/* PCH (HPET/LT/TPM/Others) */
+#define PCH_BASE_ADDRESS         0xfed00000
+#define PCH_BASE_SIZE            0x00100000
+
+/* Local XAPIC */
+#define LXAPIC_BASE_ADDRESS      0xfee00000
+#define LXAPIC_BASE_SIZE         0x00100000
+
+/* High Performance Event Timer */
+#define HPET_BASE_ADDRESS        0xfed00000
+#define HPET_BASE_SIZE           0x400
+
+/* Firmware */
+#define FIRMWARE_BASE_ADDRESS    0xff000000
+#define FIRMWARE_BASE_SIZE       0x01000000
+
+/*
+ * IO Port bases.
+ */
+
+/* ACPI Base Address */
+#define ACPI_BASE_ADDRESS        0x400
+#define ACPI_BASE_SIZE           0x80
+
+#endif /* _SOC_IOMAP_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/irq.h b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h
new file mode 100644
index 0000000000..ea043267e3
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/irq.h
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_IRQ_H_
+#define _SOC_IRQ_H_
+
+#define PIRQA_APIC_IRQ 16
+#define PIRQB_APIC_IRQ 17
+#define PIRQC_APIC_IRQ 18
+#define PIRQD_APIC_IRQ 19
+#define PIRQE_APIC_IRQ 20
+#define PIRQF_APIC_IRQ 21
+#define PIRQG_APIC_IRQ 22
+#define PIRQH_APIC_IRQ 23
+
+/* PIC IRQ settings. */
+#define PIRQ_PIC_IRQ3           0x3
+#define PIRQ_PIC_IRQ4           0x4
+#define PIRQ_PIC_IRQ5           0x5
+#define PIRQ_PIC_IRQ6           0x6
+#define PIRQ_PIC_IRQ7           0x7
+#define PIRQ_PIC_IRQ9           0x9
+#define PIRQ_PIC_IRQ10          0xa
+#define PIRQ_PIC_IRQ11          0xb
+#define PIRQ_PIC_IRQ12          0xc
+#define PIRQ_PIC_IRQ14          0xe
+#define PIRQ_PIC_IRQ15          0xf
+#define PIRQ_PIC_IRQDISABLE     0x80
+#define PIRQ_PIC_UNKNOWN_UNUSED 0xff
+
+/* Overloaded term, but these values determine the per device route. */
+#define PIRQA 0
+#define PIRQB 1
+#define PIRQC 2
+#define PIRQD 3
+#define PIRQE 4
+#define PIRQF 5
+#define PIRQG 6
+#define PIRQH 7
+
+/* In each mainboard directory there should exist a header file irqroute.h that
+ * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
+ * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */
+
+#if !defined(__ASSEMBLER__) && !defined(__ACPI__)
+#include <stdint.h>
+
+#define NUM_OF_PCI_DEVS 32
+#define NUM_PIRQS   8
+
+struct broadwell_de_irq_route {
+	/* Per device configuration. */
+	uint16_t pcidev[NUM_OF_PCI_DEVS];
+	/* Route path for each internal PIRQx in PIC mode. */
+	uint8_t  pic[NUM_PIRQS];
+};
+
+extern const struct broadwell_de_irq_route global_broadwell_de_irq_route;
+
+#define DEFINE_IRQ_ROUTES \
+	const struct broadwell_de_irq_route global_broadwell_de_irq_route = { \
+		.pcidev = { PCI_DEV_PIRQ_ROUTES, }, \
+		.pic = { PIRQ_PIC_ROUTES, }, \
+	}
+
+#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \
+	[dev_] = ((PIRQ ## d_) << 12) | ((PIRQ ## c_) << 8) | \
+	         ((PIRQ ## b_) <<  4) | ((PIRQ ## a_) << 0)
+
+#define PIRQ_PIC(pirq_, pic_irq_) \
+	[PIRQ ## pirq_] = PIRQ_PIC_IRQ ## pic_irq_
+
+#endif /* !defined(__ASSEMBLER__) && !defined(__ACPI__) */
+
+#endif /* _SOC_IRQ_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
new file mode 100644
index 0000000000..2c02ebdf47
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/lpc.h
@@ -0,0 +1,86 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_LPC_H_
+#define _SOC_LPC_H_
+
+/* LPC Interface Bridge PCI Configuration Registers */
+#define REVID			0x08
+#define PIRQ_RCR1		0x60
+#define PIRQ_RCR2		0x68
+#define GEN_PMCON_1		0xA0
+#define GEN_PMCON_2		0xA2
+#define GEN_PMCON_3		0xA4
+#define   RTC_PWR_STS		(1 << 2)
+
+/* Default IO range claimed by the LPC device. The upper bound is exclusive. */
+#define LPC_DEFAULT_IO_RANGE_LOWER 0
+#define LPC_DEFAULT_IO_RANGE_UPPER 0x1000
+
+/* IO Mapped registers behind ACPI_BASE_ADDRESS */
+#define PM1_STS			0x00
+#define   WAK_STS		(1 << 15)
+#define   PCIEXPWAK_STS		(1 << 14)
+#define   USB_STS		(1 << 13)
+#define   PRBTNOR_STS		(1 << 11)
+#define   RTC_STS		(1 << 10)
+#define   PWRBTN_STS		(1 << 8)
+#define   GBL_STS		(1 << 5)
+#define   TMROF_STS		(1 << 0)
+#define PM1_EN			0x02
+#define   PCIEXPWAK_DIS		(1 << 14)
+#define   RTC_EN		(1 << 10)
+#define   PWRBTN_EN		(1 << 8)
+#define   GBL_EN		(1 << 5)
+#define   TMROF_EN		(1 << 0)
+#define PM1_CNT			0x04
+#define   SLP_EN		(1 << 13)
+#define   SLP_TYP_SHIFT		10
+#define   SLP_TYP		(7 << SLP_TYP_SHIFT)
+#define    SLP_TYP_S0		0
+#define    SLP_TYP_S1		1
+#define    SLP_TYP_S3		5
+#define    SLP_TYP_S4		6
+#define    SLP_TYP_S5		7
+#define   GBL_RLS		(1 << 2)
+#define   BM_RLD		(1 << 1)
+#define   SCI_EN		(1 << 0)
+#define PM1_TMR			0x08
+#define GPE0_STS		0x20
+#define   PCI_EXP_STS		(1 << 9)
+#define   RI_STS		(1 << 8)
+#define   SMB_WAK_STS		(1 << 7)
+#define   TCOSCI_STS		(1 << 6)
+#define   SWGPE_STS		(1 << 2)
+#define   HOT_PLUG_STS		(1 << 1)
+#define GPE0_EN			0x28
+#define SMI_EN			0x30
+#define SMI_STS			0x34
+#define ALT_GPIO_SMI		0x38
+#define UPRWC			0x3c
+#define   UPRWC_WR_EN		(1 << 1) // USB Per-Port Registers Write Enable
+#define GPE_CTRL		0x40
+#define PM2A_CNT_BLK		0x50
+#define TCO_RLD			0x60
+#define TCO_STS			0x64
+#define   SECOND_TO_STS		(1 << 17)
+#define   TCO_TIMEOUT		(1 << 3)
+#define TCO1_CNT		0x68
+#define   TCO_LOCK		(1 << 12)
+#define   TCO_TMR_HALT		(1 << 11)
+#define TCO_TMR			0x70
+
+#endif /* _SOC_LPC_H_ */
\ No newline at end of file
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
new file mode 100644
index 0000000000..c409ec86b6
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_MSR_H_
+#define _SOC_MSR_H_
+
+#define MSR_IA32_PLATFORM_ID    0x17
+#define MSR_CORE_THREAD_COUNT   0x35
+#define MSR_PLATFORM_INFO       0xce
+#define MSR_TURBO_RATIO_LIMIT   0x1ad
+#define MSR_IA32_MC0_STATUS     0x400
+#define MSR_PKG_POWER_SKU_UNIT  0x606
+#define MSR_PKG_POWER_LIMIT     0x610
+
+#endif /* _SOC_MSR_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h
new file mode 100644
index 0000000000..232a4f4a7d
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/pattrs.h
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PATTRS_H_
+#define _SOC_PATTRS_H_
+
+#include <stdint.h>
+#include <cpu/x86/msr.h>
+
+/*
+ * The pattrs structure is a common place to stash pertinent information
+ * about the processor or platform. Instead of going to the source (msrs, cpuid)
+ * every time an attribute is needed use the pattrs structure.
+ */
+struct pattrs {
+	msr_t platform_id;
+	msr_t platform_info;
+	uint32_t cpuid;
+	int revid;
+	int stepping;
+	const void *microcode_patch;
+	int address_bits;
+	int num_cpus;
+};
+
+/*
+ * This is just to hide the abstraction w/o relying on how the underlying
+ * storage is allocated.
+ */
+#define PATTRS_GLOB_NAME __global_pattrs
+#define DEFINE_PATTRS struct pattrs PATTRS_GLOB_NAME
+extern DEFINE_PATTRS;
+
+static inline const struct pattrs *pattrs_get(void)
+{
+	return &PATTRS_GLOB_NAME;
+}
+
+#endif /* _SOC_PATTRS_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
new file mode 100644
index 0000000000..646ed3fecb
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h
@@ -0,0 +1,110 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PCI_DEVS_H_
+#define _SOC_PCI_DEVS_H_
+
+#define BUS0 0
+
+#define SOC_DEV                 0
+#define SOC_FUNC                0
+#define SOC_DEVID               0x2F00
+#define SOC_DEVID_ES2           0x6F00
+#define SOC_DEV_FUNC DEV_FUNC(SOC_DEV, SOC_FUNC)
+
+#define LPC_DEV                 31
+#define LPC_FUNC                0
+#define LPC_DEVID               0x8C42
+#define LPC_DEVID_ES2           0x8C54
+#define LPC_DEV_FUNC DEV_FUNC(LPC_DEV, LPC_FUNC)
+
+#define SATA_DEV                31
+#define SATA_FUNC               2
+#define AHCI_DEVID              0x8C02
+#define SATA_DEV_FUNC DEV_FUNC(SATA_DEV, SATA_FUNC)
+
+#define SATA2_DEV               31
+#define SATA2_FUNC              5
+#define SATA2_DEV_FUNC DEV_FUNC(SATA2_DEV, SATA2_FUNC)
+
+#define EHCI1_DEV               29
+#define EHCI1_FUNC              0
+#define EHCI1_DEVID             0x8C26
+#define EHCI1_DEV_FUNC DEV_FUNC(EHCI_DEV1, EHCI_FUNC1)
+
+#define EHCI2_DEV               26
+#define EHCI2_FUNC              0
+#define EHCI2_DEVID             0x8C2D
+#define EHCI2_DEV_FUNC DEV_FUNC(EHCI_DEV2, EHCI_FUNC2)
+
+#define XHCI_DEV                20
+#define XHCI_FUNC               0
+#define XHCI_DEVID              0x8C31
+#define XHCI_FUS_REG            0xE0
+#define XHCI_FUNC_DISABLE       (1 << 0)
+#define XHCI_USB2PR_REG         0xD0
+#define XHCI_DEV_FUNC DEV_FUNC(XHCI_DEV, XHCI_FUNC)
+
+#define GBE_DEV                 25
+#define GBE_FUNC                0
+#define GBE_DEVID               0x8C33
+#define GBE_DEV_FUNC DEV_FUNC(GBE_DEV, GBE_FUNC)
+
+#define ME_DEV                  22
+#define ME_FUNC                 0
+#define ME_DEVID                0x8C3A
+#define ME_DEV_FUNC DEV_FUNC(ME_DEV, ME_FUNC)
+
+#define HDA_DEV                 27
+#define HDA_FUNC                0
+#define HDA_DEVID               0x8C20
+#define HDA_DEV_FUNC DEV_FUNC(HDA_DEV, HDA_FUNC)
+
+#define PCIE_DEV                28
+#define PCIE_PORT1_DEV          PCIE_DEV
+#define PCIE_PORT1_FUNC         0
+#define PCIE_PORT1_DEVID        0x8C10
+#define PCIE_PORT2_DEV          PCIE_DEV
+#define PCIE_PORT2_FUNC         1
+#define PCIE_PORT2_DEVID        0x8C12
+#define PCIE_PORT3_DEV          PCIE_DEV
+#define PCIE_PORT3_FUNC         2
+#define PCIE_PORT3_DEVID        0x8C14
+#define PCIE_PORT4_DEV          PCIE_DEV
+#define PCIE_PORT4_FUNC         3
+#define PCIE_PORT4_DEVID        0x8C16
+#define PCIE_PORT5_DEV          PCIE_DEV
+#define PCIE_PORT5_FUNC         4
+#define PCIE_PORT5_DEVID        0x8C18
+#define PCIE_PORT6_DEV          PCIE_DEV
+#define PCIE_PORT6_FUNC         5
+#define PCIE_PORT6_DEVID        0x8C1A
+#define PCIE_PORT7_DEV          PCIE_DEV
+#define PCIE_PORT7_FUNC         6
+#define PCIE_PORT7_DEVID        0x8C1C
+#define PCIE_PORT8_DEV          PCIE_DEV
+#define PCIE_PORT8_FUNC         7
+#define PCIE_PORT8_DEVID        0x8C1E
+#define PCIE_PORT1_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT1_FUNC)
+#define PCIE_PORT2_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT2_FUNC)
+#define PCIE_PORT3_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT3_FUNC)
+#define PCIE_PORT4_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT4_FUNC)
+#define PCIE_PORT5_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT5_FUNC)
+#define PCIE_PORT6_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT6_FUNC)
+#define PCIE_PORT7_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT7_FUNC)
+#define PCIE_PORT8_DEV_FUNC DEV_FUNC(PCIE_DEV, PCIE_PORT8_FUNC)
+
+#endif /* _SOC_PCI_DEVS_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h
new file mode 100644
index 0000000000..c01c9ac081
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/ramstage.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RAMSTAGE_H_
+#define _SOC_RAMSTAGE_H_
+
+#include <device/device.h>
+
+/* The broadwell_de_init_pre_device() function is called prior to device
+ * initialization, but it's after console and cbmem has been reinitialized. */
+void broadwell_de_init_pre_device(void);
+void broadwell_de_init_cpus(device_t dev);
+void southcluster_enable_dev(device_t dev);
+
+extern struct pci_operations soc_pci_ops;
+
+#endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/reset.h b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
new file mode 100644
index 0000000000..fa0ceac091
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/reset.h
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_RESET_H_
+#define _SOC_RESET_H_
+
+#include <reset.h>
+
+void warm_reset(void);
+
+#endif /* _SOC_RESET_H_ */
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h
new file mode 100644
index 0000000000..94a5a5669c
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/romstage.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#if !defined(__PRE_RAM__)
+#error "Don't include romstage.h from a ramstage compilation unit!"
+#endif
+
+#include <stdint.h>
+#include <arch/cpu.h>
+#include <fsp.h>
+
+void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr);
+
+#define NUM_ROMSTAGE_TS 4
+
+void early_mainboard_romstage_entry(void);
+void late_mainboard_romstage_entry(void);
+
+#endif /* _SOC_ROMSTAGE_H_ */