diff options
| author | Werner Zeh <werner.zeh@siemens.com> | 2016-07-12 07:10:19 +0200 |
|---|---|---|
| committer | Werner Zeh <werner.zeh@siemens.com> | 2016-07-14 07:03:40 +0200 |
| commit | 7804790226276dce0bf9c659bba061d46b5a184a (patch) | |
| tree | c81fb2d3e36bdd474bd777db6f9dc1e2fb48d48b /src/soc/intel/fsp_broadwell_de/include | |
| parent | bc62834306e93198741c36c19ea2cda7e0537cc4 (diff) | |
fsp_broadwell_de: Add SMBus driver for ramstage
There is currently a SMBus driver implemented for soc/intel/broadwell
which nearly matches Broadwell-DE as well. Use this driver as template
and add minor modifications to make it work for Broadwell-DE. Support in
romstage is not available and can be added with a different patch.
Change-Id: I64649ceaa298994ee36018f5b2b0f5d49cf7ffd0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/15617
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/include')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h | 5 | ||||
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/include/soc/smbus.h | 48 |
2 files changed, 53 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h index 99236018c5..5f3cfb963a 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/pci_devs.h @@ -38,6 +38,11 @@ #define AHCI_DEVID 0x8C02 #define SATA_DEV_FUNC PCI_DEVFN(SATA_DEV, SATA_FUNC) +#define SMBUS_DEV 31 +#define SMBUS_FUNC 3 +#define SMBUS_DEVID 0x8C22 +#define SMBUS_DEV_FUNC PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC) + #define SATA2_DEV 31 #define SATA2_FUNC 5 #define SATA2_DEV_FUNC PCI_DEVFN(SATA2_DEV, SATA2_FUNC) diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h new file mode 100644 index 0000000000..0a7dbaeeab --- /dev/null +++ b/src/soc/intel/fsp_broadwell_de/include/soc/smbus.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Yinghai Lu <yinghailu@gmail.com> + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _BROADWELL_SMBUS_H_ +#define _BROADWELL_SMBUS_H_ + +/* PCI Configuration Space (D31:F3): SMBus */ +#define SMB_BASE 0x20 +#define HOSTC 0x40 +#define HST_EN (1 << 0) +#define SMB_RCV_SLVA 0x09 + +/* SMBus I/O bits. */ +#define SMBHSTSTAT 0x0 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf + +#define SMBUS_TIMEOUT (10 * 1000 * 100) +#define SMBUS_SLAVE_ADDR 0x24 + +int do_smbus_read_byte(unsigned smbus_base, unsigned device, + unsigned address); +int do_smbus_write_byte(unsigned smbus_base, unsigned device, + unsigned address, unsigned data); + +#endif |