soc/intel: Add Broadwell-DE SoC support

Initial files to support Broadwell-DE SoC. This is FSP 1.0 based
project and is based on Broadwell-DE Gold release. Change has been
verified on Intel Camelback Mountain CRB.

Change-Id: I20ce8ee8dd1113a7a20a96910292697421f1ca57
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: https://review.coreboot.org/14014
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>

4 files changed, 271 insertions, 0 deletions

diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
new file mode 100644
index 0000000000..2e1ebebd44
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig
@@ -0,0 +1,93 @@
+config BROADWELL_DE_FSP_SPECIFIC_OPTIONS
+	def_bool y
+	select PLATFORM_USES_FSP1_0
+	select USE_GENERIC_FSP_CAR_INC
+	select FSP_USES_UPD
+
+config FSP_FILE
+	string
+	default "../intel/fsp/broadwell_de/BROADWELLDE_FSP.bin"
+	help
+	  The path and filename of the Intel FSP binary for this platform.
+
+config FSP_LOC
+	hex
+	default 0xffeb0000
+	help
+	  The location in CBFS that the FSP is located. This must match the
+	  value that is set in the FSP binary.  If the FSP needs to be moved,
+	  rebase the FSP with Intel's BCT (tool).
+
+	  The Broadwell-DE FSP is built with a preferred base address of
+	  0xffeb0000.
+
+config FSP_MEMORY_DOWN
+	bool "Enable Memory Down"
+	default n
+	help
+	  Load SPD data from ROM instead of trying to read from SMBus.
+
+	  If the platform has DIMM sockets, say N. If memory is down, say Y and
+	  supply the appropriate SPD data for each Channel/DIMM.
+
+config FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
+	bool "Channel 0, DIMM 0 Present"
+	default n
+	depends on FSP_MEMORY_DOWN
+	help
+	  Select Y if Channel 0, DIMM 0 is present.
+
+config FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE
+	string "Channel 0, DIMM 0 SPD File"
+	default "spd_ch0_dimm0.bin"
+	depends on FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT
+	help
+	  Path to the file which contains the SPD data for Channel 0, DIMM 0.
+
+config FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
+	bool "Channel 0, DIMM 1 Present"
+	default n
+	depends on FSP_MEMORY_DOWN
+	help
+	  Select Y if Channel 0, DIMM 1 is present.
+
+config FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE
+	string "Channel 0, DIMM 1 SPD File"
+	default "spd_ch0_dimm1.bin"
+	depends on FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT
+	help
+	  Path to the file which contains the SPD data for Channel 0, DIMM 1.
+
+config FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
+	bool "Channel 1, DIMM 0 Present"
+	default n
+	depends on FSP_MEMORY_DOWN
+	help
+	  Select Y if Channel 1, DIMM 0 is present.
+
+config FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE
+	string "Channel 1, DIMM 0 SPD File"
+	default "spd_ch1_dimm0.bin"
+	depends on FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT
+	help
+	  Path to the file which contains the SPD data for Channel 1, DIMM 0.
+
+config FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
+	bool "Channel 1, DIMM 1 Present"
+	default n
+	depends on FSP_MEMORY_DOWN
+	help
+	  Select Y if Channel 1, DIMM 1 is present.
+
+config FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE
+	string "Channel 1, DIMM 1 SPD File"
+	default "spd_ch1_dimm1.bin"
+	depends on FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT
+	help
+	  Path to the file which contains the SPD data for Channel 1, DIMM 1.
+
+config FSP_HYPERTHREADING
+	bool "Enable Hyper-Threading"
+	default y
+	help
+	  Enable Intel(r) Hyper-Threading Technology for the Broadwell-DE SoC.
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc b/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc
new file mode 100644
index 0000000000..651976483e
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/fsp/Makefile.inc
@@ -0,0 +1,17 @@
+romstage-y += chipset_fsp_util.c
+
+cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT) += spd_ch0_dimm0.bin
+spd_ch0_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_FILE))
+spd_ch0_dimm0.bin-type := spd
+
+cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT) += spd_ch0_dimm1.bin
+spd_ch0_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_FILE))
+spd_ch0_dimm1.bin-type := spd
+
+cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT) += spd_ch1_dimm0.bin
+spd_ch1_dimm0.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_FILE))
+spd_ch1_dimm0.bin-type := spd
+
+cbfs-files-$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT) += spd_ch1_dimm1.bin
+spd_ch1_dimm1.bin-file := $(call strip_quotes,$(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_FILE))
+spd_ch1_dimm1.bin-type := spd
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
new file mode 100644
index 0000000000..cab4b5919c
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
@@ -0,0 +1,126 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <bootstate.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <drivers/intel/fsp1_0/fsp_util.h>
+#include <soc/pci_devs.h>
+#include <soc/reset.h>
+#include <soc/romstage.h>
+#include <chip.h>
+#include <fsp.h>
+
+/* Copy the default UPD region and settings to a buffer for modification */
+static void GetUpdDefaultFromFsp (FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *UpdData)
+{
+	VPD_DATA_REGION *VpdDataRgnPtr;
+	UPD_DATA_REGION *UpdDataRgnPtr;
+	VpdDataRgnPtr = (VPD_DATA_REGION *)(UINT32)(FspInfo->CfgRegionOffset  + FspInfo->ImageBase);
+	UpdDataRgnPtr = (UPD_DATA_REGION *)(UINT32)(VpdDataRgnPtr->PcdUpdRegionOffset + FspInfo->ImageBase);
+	memcpy((void *)UpdData, (void *)UpdDataRgnPtr, sizeof(UPD_DATA_REGION));
+}
+
+typedef struct soc_intel_fsp_broadwell_de_config config_t;
+
+/**
+ * Update the UPD data based on values from devicetree.cb
+ *
+ * @param UpdData Pointer to the UPD Data structure
+ */
+static void ConfigureDefaultUpdData(UPD_DATA_REGION *UpdData)
+{
+	/*
+	 * Serial Port
+	 */
+	if (IS_ENABLED(CONFIG_INTEGRATED_UART))
+		UpdData->SerialPortConfigure = 1;
+
+	/*
+	 * Memory Down
+	 */
+	if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN)) {
+		UpdData->MemDownEnable = 1;
+
+		if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM0_SPD_PRESENT))
+			UpdData->MemDownCh0Dimm0SpdPtr
+			= (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm0.bin", CBFS_TYPE_RAW, NULL);
+		if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH0DIMM1_SPD_PRESENT))
+			UpdData->MemDownCh0Dimm1SpdPtr
+			= (UINT32)cbfs_boot_map_with_leak("spd_ch0_dimm1.bin", CBFS_TYPE_RAW, NULL);
+		if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM0_SPD_PRESENT))
+			UpdData->MemDownCh1Dimm0SpdPtr
+			= (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm0.bin", CBFS_TYPE_RAW, NULL);
+		if (IS_ENABLED(CONFIG_FSP_MEMORY_DOWN_CH1DIMM1_SPD_PRESENT))
+			UpdData->MemDownCh1Dimm1SpdPtr
+			= (UINT32)cbfs_boot_map_with_leak("spd_ch1_dimm1.bin", CBFS_TYPE_RAW, NULL);
+	} else {
+		UpdData->MemDownEnable = 0;
+	}
+	printk(FSP_INFO_LEVEL, "Memory Down Support: %s\n",
+		UpdData->MemDownEnable ? "Enabled" : "Disabled");
+
+	/*
+	 * Fast Boot
+	 */
+	if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE))
+		UpdData->MemFastBoot = 1;
+	else
+		UpdData->MemFastBoot = 0;
+
+	/*
+	 * Hyper-Threading
+	 */
+	if (IS_ENABLED(CONFIG_FSP_HYPERTHREADING))
+		UpdData->HyperThreading = 1;
+	else
+		UpdData->HyperThreading = 0;
+}
+
+/* Set up the Broadwell-DE specific structures for the call into the FSP */
+void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr)
+{
+	FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr;
+
+	/* Initialize the UPD Data */
+	GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr);
+	ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr);
+	pFspInitParams->NvsBufferPtr = NULL;
+
+#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
+	/* Find the fastboot cache that was saved in the ROM */
+	pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache();
+#endif
+
+	return;
+}
+
+/* The FSP returns here after the fsp_early_init call */
+void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr)
+{
+	*(void **)CBMEM_FSP_HOB_PTR = HobListPtr;
+
+	if (Status == 0xFFFFFFFF) {
+		warm_reset();
+	}
+
+	romstage_main_continue(Status, HobListPtr);
+}
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h
new file mode 100644
index 0000000000..057d7fda0d
--- /dev/null
+++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.h
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef CHIPSET_FSP_UTIL_H
+#define CHIPSET_FSP_UTIL_H
+
+#include <fsp.h>
+
+#define FSP_INFO_HEADER_GUID \
+  { \
+  0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
+  }
+
+/*
+ * The FSP Image ID is different for each platform's FSP and
+ * can be used to verify that the right FSP binary is loaded.
+ * For the Broadwell-DE FSP, the Image Id is "BDX-DE".
+ */
+#define FSP_IMAGE_ID_DWORD0 ((unsigned int)(FSP_IMAGE_ID))
+#define FSP_IMAGE_ID_DWORD1 ((unsigned int)(FSP_IMAGE_ID >> 32))
+
+#endif /* CHIPSET_FSP_UTIL_H */