diff options
| author | Patrick Rudolph <siro@das-labor.org> | 2018-10-01 19:17:11 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-10-22 08:35:25 +0000 |
| commit | 45022ae056cdbf58429b77daf2da176306312801 (patch) | |
| tree | 4218666e3c14e41232778c4ceff301292b3c61d9 /src/soc/intel/fsp_broadwell_de/fsp | |
| parent | 33fcaf91ff825ad0adf0a2a483e6a296ed4e0e31 (diff) | |
intel: Use CF9 reset (part 1)
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/fsp')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 148ffdc367..800f68653b 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -20,11 +20,11 @@ #include <bootstate.h> #include <cbfs.h> #include <cbmem.h> +#include <cf9_reset.h> #include <device/device.h> #include <device/pci_def.h> #include <drivers/intel/fsp1_0/fsp_util.h> #include <soc/pci_devs.h> -#include <soc/reset.h> #include <soc/romstage.h> #include <chip.h> #include <fsp.h> @@ -142,7 +142,7 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) *(void **)CBMEM_FSP_HOB_PTR = HobListPtr; if (Status == 0xFFFFFFFF) { - warm_reset(); + system_reset(); } romstage_main_continue(Status, HobListPtr); |