diff options
| author | David Hendricks <dhendricks@fb.com> | 2018-03-06 18:48:44 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-28 09:05:19 +0000 |
| commit | 0ea93cdc35d4e49b416c9c73093d722c0a7bd860 (patch) | |
| tree | 64400f5cbb72eb10c40b7983dcea1b018b58b91f /src/soc/intel/fsp_broadwell_de/Makefile.inc | |
| parent | 7bea0846db3ba262512a36170e8ea38135522001 (diff) | |
fsp_broadwell_de: Add ability to set PCIe completion timeout
This enables the user to set the completion timeout value in PCI
Express Device Control 2 register via devicetree.cb.
Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release.
Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/fsp_broadwell_de/Makefile.inc')
| -rw-r--r-- | src/soc/intel/fsp_broadwell_de/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/fsp_broadwell_de/Makefile.inc b/src/soc/intel/fsp_broadwell_de/Makefile.inc index fc6cdd3d42..024035cef9 100644 --- a/src/soc/intel/fsp_broadwell_de/Makefile.inc +++ b/src/soc/intel/fsp_broadwell_de/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += smbus.c romstage-y += tsc_freq.c ramstage-y += smi.c ramstage-y += gpio.c +ramstage-y += iou_complto.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c smm-$(CONFIG_HAVE_SMI_HANDLER) += pmutil.c |