Move baytrail & fsp_baytrail to the common IFD interface.

- Add the common/firmware subdir to the baytrail & fsp_baytrail
makefiles and remove the code it replaces.
- Update baytrail & fsp_baytrail Kconfigs to use the common code.
- Update the IFD Kconfig help and prompts for the TXE vs ME.
- Whittle away at the CBFS_SIZE defaults.  All the fsp_baytrail
platforms have their own defaults.

Change-Id: I96a9d4acd6578225698dba28d132d203b8fb71a0
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10647
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

2 files changed, 2 insertions, 57 deletions

diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig
index 95d45da657..d51a238f0d 100644
--- a/src/soc/intel/fsp_baytrail/Kconfig
+++ b/src/soc/intel/fsp_baytrail/Kconfig
@@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS
 	select TSC_SYNC_MFENCE
 	select UDELAY_TSC
 	select SUPPORT_CPU_UCODE_IN_CBFS
+	select HAVE_INTEL_FIRMWARE
 
 config SOC_INTEL_FSP_BAYTRAIL_MD
 	bool
@@ -94,34 +95,6 @@ config CPU_MICROCODE_CBFS_LOC
 	hex
 	default 0xfff10040
 
-config INCLUDE_ME
-	bool "Include the TXE"
-	default n
-	help
-	  Build the TXE and descriptor.bin into the ROM image.  If you want to use a
-	  descriptor.bin and TXE file from the previous ROM image, you may not want
-	  to build it in here.
-
-config ME_PATH
-	string "Path to ME"
-	depends on INCLUDE_ME
-	help
-	  The path of the TXE and Descriptor files.
-
-config LOCK_MANAGEMENT_ENGINE
-	bool "Lock TXE section"
-	default n
-	depends on INCLUDE_ME
-	help
-	  The Intel Trusted Execution Engine supports preventing write accesses
-	  from the host to the Management Engine section in the firmware
-	  descriptor. If the ME section is locked, it can only be overwritten
-	  with an external SPI flash programmer. You will want this if you
-	  want to increase security of your ROM image once you are sure
-	  that the ME firmware is no longer going to change.
-
-	  If unsure, say N.
-
 config ENABLE_BUILTIN_COM1
 	bool "Enable built-in legacy Serial Port"
 	help
diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc
index 92a1fbd988..45ea3e418d 100644
--- a/src/soc/intel/fsp_baytrail/Makefile.inc
+++ b/src/soc/intel/fsp_baytrail/Makefile.inc
@@ -30,6 +30,7 @@ subdirs-y += ../../../cpu/x86/cache
 subdirs-y += ../../../cpu/intel/turbo
 subdirs-y += ../../../lib/fsp
 subdirs-y += fsp
+subdirs-y += ../../../southbridge/intel/common/firmware
 
 ramstage-y += memmap.c
 romstage-y += memmap.c
@@ -62,33 +63,4 @@ ramstage-y += i2c.c
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/
 CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp
 
-# Run an intermediate step when producing coreboot.rom
-# that adds additional components to the final firmware
-# image outside of CBFS
-ifeq ($(CONFIG_INCLUDE_ME),y)
-ifneq ($(CONFIG_ME_PATH),)
-INTERMEDIATE:=baytrail_add_txe
-
-baytrail_add_txe: $(obj)/coreboot.pre $(IFDTOOL)
-	printf "    DD         Adding Intel Firmware Descriptor\n"
-	dd if=$(call strip_quotes,$(CONFIG_ME_PATH))/descriptor.bin \
-		of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
-	printf "    IFDTOOL    txe.bin -> coreboot.pre\n"
-	$(objutil)/ifdtool/ifdtool \
-		-i ME:$(call strip_quotes,$(CONFIG_ME_PATH))/txe.bin \
-		$(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
-	printf "    IFDTOOL    Locking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -l $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-else
-	printf "    IFDTOOL    Unlocking Management Engine\n"
-	$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
-	mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
-endif
-
-endif
-endif
-
 endif