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| author | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-09-30 20:23:09 -0700 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-10-15 03:52:49 +0000 |
| commit | 86091f94b6ca58f4b8795503b274492d6a935c15 (patch) | |
| tree | db6e5f77dc57850b25574aed5063743ca4bc4d48 /src/soc/intel/fsp_baytrail | |
| parent | 58562405c8c416a415652516b8af31b204b4ff0d (diff) | |
cpu/mtrr.h: Fix macro names for MTRR registers
We use UNDERSCORE_CASE. For the MTRR macros that refer to an MSR,
we also remove the _MSR suffix, as they are, by definition, MSRs.
Change-Id: Id4483a75d62cf1b478a9105ee98a8f55140ce0ef
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11761
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/soc/intel/fsp_baytrail')
| -rw-r--r-- | src/soc/intel/fsp_baytrail/bootblock/bootblock.c | 8 | ||||
| -rw-r--r-- | src/soc/intel/fsp_baytrail/cpu.c | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c index 50d321bccc..41b911e690 100644 --- a/src/soc/intel/fsp_baytrail/bootblock/bootblock.c +++ b/src/soc/intel/fsp_baytrail/bootblock/bootblock.c @@ -52,10 +52,10 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type) msr_t basem, maskm; basem.lo = base | type; basem.hi = 0; - wrmsr(MTRRphysBase_MSR(reg), basem); - maskm.lo = ~(size - 1) | MTRRphysMaskValid; + wrmsr(MTRR_PHYS_BASE(reg), basem); + maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRRphysMask_MSR(reg), maskm); + wrmsr(MTRR_PHYS_MASK(reg), maskm); } /* @@ -80,7 +80,7 @@ static void enable_rom_caching(void) /* Enable Variable MTRRs */ msr.hi = 0x00000000; msr.lo = 0x00000800; - wrmsr(MTRRdefType_MSR, msr); + wrmsr(MTRR_DEF_TYPE_MSR, msr); } static void setup_mmconfig(void) diff --git a/src/soc/intel/fsp_baytrail/cpu.c b/src/soc/intel/fsp_baytrail/cpu.c index c7ee5825d7..8fe1df36b2 100644 --- a/src/soc/intel/fsp_baytrail/cpu.c +++ b/src/soc/intel/fsp_baytrail/cpu.c @@ -173,10 +173,10 @@ static void asmlinkage cpu_smm_do_relocation(void *arg) /* Set up SMRR. */ smrr.lo = relo_attrs.smrr_base; smrr.hi = 0; - wrmsr(SMRRphysBase_MSR, smrr); + wrmsr(SMRR_PHYS_BASE, smrr); smrr.lo = relo_attrs.smrr_mask; smrr.hi = 0; - wrmsr(SMRRphysMask_MSR, smrr); + wrmsr(SMRR_PHYS_MASK, smrr); /* The relocated handler runs with all CPUs concurrently. Therefore * stagger the entry points adjusting SMBASE downwards by save state @@ -243,7 +243,7 @@ static int smm_load_handlers(void) relo_attrs.smbase = (uint32_t)smm_region_start(); relo_attrs.smrr_base = relo_attrs.smbase | MTRR_TYPE_WRBACK; relo_attrs.smrr_mask = ~(smm_region_size() - 1) & rmask; - relo_attrs.smrr_mask |= MTRRphysMaskValid; + relo_attrs.smrr_mask |= MTRR_PHYS_MASK_VALID; /* Install handlers. */ if (install_relocation_handler(pattrs->num_cpus) < 0) { |